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Volumn , Issue , 2008, Pages 182-187

Analysis of the test data volume reduction benefit of modular SOC testing

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN OF EXPERIMENTS; IMPACT TESTING; INDUSTRIAL ENGINEERING; PROGRAMMABLE LOGIC CONTROLLERS; TEST FACILITIES; TESTING;

EID: 47849112520     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484683     Document Type: Conference Paper
Times cited : (6)

References (25)
  • 4
    • 0032688229 scopus 로고    scopus 로고
    • Challenges in Testing Core-Based System ICs
    • June
    • Erik Jan Marinissen and Yervant Zorian, "Challenges in Testing Core-Based System ICs", IEEE Communications Magazine, vol. 37, n. 6, pp. 104-109, June 1999.
    • (1999) IEEE Communications Magazine , vol.37 , Issue.6 , pp. 104-109
    • Jan Marinissen, E.1    Zorian, Y.2
  • 10
    • 0032308284 scopus 로고    scopus 로고
    • A Structured Test Re-Use Methodology for Core-Based System Chips
    • Washington, DC, USA, October
    • Prab Varma and Sandeep Bhatia, "A Structured Test Re-Use Methodology for Core-Based System Chips", in Proceedings IEEE International Test Conference (ITC), pp. 294-302, Washington, DC, USA, October 1998.
    • (1998) Proceedings IEEE International Test Conference (ITC) , pp. 294-302
    • Varma, P.1    Bhatia, S.2
  • 11
    • 0032320505 scopus 로고    scopus 로고
    • A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores
    • Washington, DC, USA, October
    • Erik Jan Marinissen et al., "A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores", in Proceedings IEEE International Test Conference (ITC), pp. 284-293, Washington, DC, USA, October 1998.
    • (1998) Proceedings IEEE International Test Conference (ITC) , pp. 284-293
    • Jan Marinissen, E.1
  • 12
    • 0032314038 scopus 로고    scopus 로고
    • Scan Chain Design for Test Time Reduction in Core-Based ICs
    • Washington, DC, USA, October
    • Joep Aerts and Erik Jan Marinissen, "Scan Chain Design for Test Time Reduction in Core-Based ICs", in Proceedings IEEE International Test Conference (ITC), pp. 448-457, Washington, DC, USA, October 1998.
    • (1998) Proceedings IEEE International Test Conference (ITC) , pp. 448-457
    • Aerts, J.1    Jan Marinissen, E.2
  • 15
    • 18144423550 scopus 로고    scopus 로고
    • Integrating Core Selection in the SOC Test Solution Design-Flow
    • Charlotte, NC, USA, October
    • Erik Larsson, "Integrating Core Selection in the SOC Test Solution Design-Flow", in Proceedings IEEE International Test Conference (ITC), pp. 1349-1358, Charlotte, NC, USA, October 2004.
    • (2004) Proceedings IEEE International Test Conference (ITC) , pp. 1349-1358
    • Larsson, E.1
  • 17
    • 0034995151 scopus 로고    scopus 로고
    • Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
    • Marina del Rey, CA, USA, May
    • Vikram Iyengar and Krishnendu Chakrabarty, "Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip", in Proceedings IEEE VLSI Test Symposium (VTS), pp. 368-374, Marina del Rey, CA, USA, May 2001.
    • (2001) Proceedings IEEE VLSI Test Symposium (VTS) , pp. 368-374
    • Iyengar, V.1    Chakrabarty, K.2
  • 18
    • 0035704354 scopus 로고    scopus 로고
    • Test Scheduling and Scan-Chain Division Under Power Constraint
    • Kyoto, Japan, November
    • Erik Larsson and Zebo Peng, "Test Scheduling and Scan-Chain Division Under Power Constraint", in Proceedings IEEE Asian Test Symposium (ATS), pp. 259-264, Kyoto, Japan, November 2001.
    • (2001) Proceedings IEEE Asian Test Symposium (ATS) , pp. 259-264
    • Larsson, E.1    Peng, Z.2
  • 19
    • 84949754675 scopus 로고    scopus 로고
    • Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
    • Tamuning, Guam, USA, November
    • Vikram Iyengar, Krishnendu Chakrabarty and Erik Jan Marinissen, "Recent Advances in Test Planning for Modular Testing of Core-Based SOCs", in Proceedings IEEE Asian Test Symposium (ATS), pp. 320-325, Tamuning, Guam, USA, November 2002.
    • (2002) Proceedings IEEE Asian Test Symposium (ATS) , pp. 320-325
    • Iyengar, V.1    Chakrabarty, K.2    Jan Marinissen, E.3
  • 25
    • 49749132612 scopus 로고    scopus 로고
    • H. K. Lee D. S. Ha, Technical Report: On the Generation of Test Patterns for Combinational Circuits, Department of Electrical Eng., Virginia Polytechnic Institute and State University, December 1993.
    • H. K. Lee D. S. Ha, "Technical Report: On the Generation of Test Patterns for Combinational Circuits", Department of Electrical Eng., Virginia Polytechnic Institute and State University, December 1993.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.