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Scheduling tests for VLSI systems under power constraints
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R. M. Chou, K. K. Saluja and V. D. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints", Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
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A gated clock scheme for low power scan testing of logic ICs or embedded cores
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November
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Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, "A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores", Proceedings of Asian Test Symposium (ATS), pp. 253-258, November 2001.
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Scheduling Algorithms
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Logic BIST for large industrial designs: Real issues and case studies
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September
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G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, "Logic BIST for Large Industrial Designs: Real Issues and Case Studies", Proceedings of International Test Conference (ITC), pp. 358-367, September 1999.
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Hetherington, G.1
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Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip
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V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip", Transactions on Computers, December 2003 (Vol. 52, No. 12), pp. 1619-1632.
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Co-optimization of test wrapper and test access architecture for embedded cores
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April
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V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Co-Optimization of Test Wrapper and Test Access Architecture for Embedded Cores", Journal of Electronic Testing; Theory and Applications (JETTA), pp 213-230, April 2002.
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A hybrid BIST architecture and its optimization for SoC testing
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March
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G. Jervan, Z. Peng, R. Ubar, and H. Kruus, "A Hybrid BIST Architecture and its Optimization for SoC Testing", Proceedings of International Symposium on Quality Electronic Design (ISQED'02), pp. 273-279, March 2002.
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Jervan, G.1
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9
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Test time minimization for hybrid BIST of core-based systems
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Xian, China, November 17-19
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G. Jervan, P. Eles, Z. Peng, R. Ubar, and M. Jenihhin, "Test Time Minimization for Hybrid BIST of Core-Based Systems", Asian Test Symposium (ATS'03), Xian, China, November 17-19, 2003, pp. 318-323.
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Test resource partitioning and optimization for SOC designs
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Napa, USA, 27 April - 1 May
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E. Larsson and H. Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs", Proceedings of VLSI Test Symposium (VTS'03), Napa, USA, 27 April - 1 May 2003, pp. 319-324.
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May
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E. Larsson, K. Arvidsson, H. Fujiwara, and Z. Peng, "Efficient Test Solutions for Core-based Designs", Transactions on CAD of Integrated Circuits and Systems, pp. 758-775, May 2004.
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An analysis of power reduction techniques in scan testing
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Oct.
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J. Saxena, K. M. Butler, and L. Whetsel, "An Analysis of Power Reduction Techniques in Scan Testing", Proc. of International Test Conference (ITC), pp. 670-677, Oct. 2001.
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Analysis and minimization of test time in a combined BIST and external test approach
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March
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M. Sugihara, H. Date, and H. Yasuura, "Analysis and Minimization of Test Time in a Combined BIST and External Test Approach", Proceedings of Design and Test in Europe (DATE), pp. 134-140, March 2000.
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Proceedings of Design and Test in Europe (DATE)
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Sugihara, M.1
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14
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A distributed BIST control scheme for complex VLSI devices
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April
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Y. Zorian, "A distributed BIST control scheme for complex VLSI devices", Proceedings of VLSI Test Symposium (VTS), pp. 4-9, April 1993.
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Testing embedded-core based system chips
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October 1998
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Y. Zorian, E. J. Marinissen, and S. Dey, S., "Testing Embedded-Core Based System Chips", Proceedings of International Test Conference (ITC), 1998, pp. 130 - 143, October 1998.
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