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Volumn , Issue , 2004, Pages 1349-1358

Integrating core selection in the SOC test solution design-flow

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; BUILT-IN SELF TEST; COMPUTATIONAL METHODS; COSTS; ESTIMATION; MATHEMATICAL MODELS; OPTIMIZATION; PROBLEM SOLVING; SCHEDULING;

EID: 18144423550     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (15)
  • 1
    • 0031163752 scopus 로고    scopus 로고
    • Scheduling tests for VLSI systems under power constraints
    • June
    • R. M. Chou, K. K. Saluja and V. D. Agrawal, "Scheduling Tests for VLSI Systems Under Power Constraints", Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
    • (1997) Transactions on VLSI Systems , vol.5 , Issue.2 , pp. 175-185
    • Chou, R.M.1    Saluja, K.K.2    Agrawal, V.D.3
  • 3
    • 84891459569 scopus 로고    scopus 로고
    • Springer-Verlag, ISBN 3-540-64105-X
    • P. Brucker, "Scheduling Algorithms", Springer-Verlag, ISBN 3-540-64105-X, 1998.
    • (1998) Scheduling Algorithms
    • Brucker, P.1
  • 6
    • 0346119949 scopus 로고    scopus 로고
    • Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip
    • December
    • V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip", Transactions on Computers, December 2003 (Vol. 52, No. 12), pp. 1619-1632.
    • (2003) Transactions on Computers , vol.52 , Issue.12 , pp. 1619-1632
    • Iyengar, V.1    Chakrabarty, K.2    Marinissen, E.J.3
  • 9
    • 84954435426 scopus 로고    scopus 로고
    • Test time minimization for hybrid BIST of core-based systems
    • Xian, China, November 17-19
    • G. Jervan, P. Eles, Z. Peng, R. Ubar, and M. Jenihhin, "Test Time Minimization for Hybrid BIST of Core-Based Systems", Asian Test Symposium (ATS'03), Xian, China, November 17-19, 2003, pp. 318-323.
    • (2003) Asian Test Symposium (ATS'03) , pp. 318-323
    • Jervan, G.1    Eles, P.2    Peng, Z.3    Ubar, R.4    Jenihhin, M.5
  • 10
    • 84943549327 scopus 로고    scopus 로고
    • Test resource partitioning and optimization for SOC designs
    • Napa, USA, 27 April - 1 May
    • E. Larsson and H. Fujiwara, "Test Resource Partitioning and Optimization for SOC Designs", Proceedings of VLSI Test Symposium (VTS'03), Napa, USA, 27 April - 1 May 2003, pp. 319-324.
    • (2003) Proceedings of VLSI Test Symposium (VTS'03) , pp. 319-324
    • Larsson, E.1    Fujiwara, H.2
  • 13
    • 84893689452 scopus 로고    scopus 로고
    • Analysis and minimization of test time in a combined BIST and external test approach
    • March
    • M. Sugihara, H. Date, and H. Yasuura, "Analysis and Minimization of Test Time in a Combined BIST and External Test Approach", Proceedings of Design and Test in Europe (DATE), pp. 134-140, March 2000.
    • (2000) Proceedings of Design and Test in Europe (DATE) , pp. 134-140
    • Sugihara, M.1    Date, H.2    Yasuura, H.3
  • 14
    • 0002129847 scopus 로고
    • A distributed BIST control scheme for complex VLSI devices
    • April
    • Y. Zorian, "A distributed BIST control scheme for complex VLSI devices", Proceedings of VLSI Test Symposium (VTS), pp. 4-9, April 1993.
    • (1993) Proceedings of VLSI Test Symposium (VTS) , pp. 4-9
    • Zorian, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.