A non-intrusive isolation approach for soft cores

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 27-32

  Sinanoglu, Ozgur ^a   Petrov, Tsvetomir ^b  

^a KUWAIT UNIVERSITY   (Kuwait)

^b QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL EFFICIENCY; CONTROLLABILITY; DATABASE SYSTEMS; INPUT OUTPUT PROGRAMS; INTERFACES (COMPUTER);

INTERFACE REGISTERS; ISOLATION TECHNIQUES;

MICROPROCESSOR CHIPS;

EID: 34548295449     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364562     Document Type: Conference Paper

References (7)

1. IEEE Std 1500-2005, "IEEE Standard Testability Method for Embedded Core-based Integrated Circuits".
2. Y. Zorian, E. J. Marinissen and S. Dey, "Testing Embedded-Core Based System Chips", in ITC, pp. 130-143, 1998.
3. N. A. Touba and B. Pouya, "Using Partial Isolation Rings to Test Core-Based Designs", IEEE Design and Test of Computers, pp. 52-59, October 1997.
4. S. Bhatia, T. Gheewala and P. Varma, "A Unifying Methodology for Intellectual Property and Custom Logic Testing", in ITC, pp. 639-648, 1996.
5. I. Ghosh, N. K. Jha and S. Dey, "A Low Overhead Design for Testability and Test Generation Technique for Core-Based Systems-on-a- Chip", IEEE TCAD, vol. 18, n. 11, pp. 1661-1676, November 1999.
6. J. Remmers, M. Villalba, and R. Fisette, "Hierarchical DFT methodology - a case study", in ITC, pp. 847-856, 2004.
7. S. Pateras, "Achieving At-speed Structural Test", IEEE Design and Test of Computers, pp. 26-33, September-October 2003.