Hierarchy-aware and area-efficient test infrastructure design for core-based system chips

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Sehgal, Anuja ^a   Goel, Sandeep Kumar ^b   Marinissen, Erik Jan ^b   Chakrabarty, Krishnendu ^c  

^a ADVANCED MICRO DEVICES   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c DUKE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER ARCHITECTURE; COSTS; OPTIMIZATION; SYSTEMS ANALYSIS;

SYSTEM INTEGRATORS; TEST ACCESS MECHANISM (TAM); TEST SCHEDULING;

INTEGRATED CIRCUIT LAYOUT;

EID: 34047131801     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244140     Document Type: Conference Paper

References (15)

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