Fast analytic placement using minimum cost flow

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 128-134

  Agnihotri, Ameya R ^a   Madden, Patrick H ^a  

^a State University of New York   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTIC PLACEMENT; CONTINUOUS AND DISCRETE OPTIMIZATION; DESIGN AUTOMATION CONFERENCE (DAC); EXPONENTIAL FUNCTIONS; MINIMUM COST FLOWS; NETWORK FLOWS; PLACEMENT PROBLEMS; RUN TIMES; SOUTH PACIFIC; WHITE SPACE; WIRE LENGTHS;

COMPUTER AIDED DESIGN; COST ACCOUNTING; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MECHANIZATION; WIRE;

INDUSTRIAL ENGINEERING;

EID: 46649096039     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.357974     Document Type: Conference Paper

References (21)

1. A. R. Agnihotri, S. Ono, C. Li, M. C. Yildiz, A. Khatkhate, C.-K. Koh, and P. H. Madden. Mixed block placement via fractional cut recursive bisection. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(5):748-761, 2005.
2. R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. Network Flows. Prentice Hall, 1993.
3. U. Brenner, A. Pauli, and J. Vygen. Almost optimum placement legalization by minimum cost flow and dynamic programming. In Proc. Int. Symp. on Physical Design, pages 2-9, 2004.
4. U. Brenner and M. Struzyna. Faster and better global placement by a new transprotation algorithm. In Proc. Design Automation Conf, pages 591-596, 2005.
5. T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. mpl6: enhanced multilevel mixed-size placement. In Proc. Int. Symp. on Physical Design, pages 212-214, 2006.
6. T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y-W. Chang. Ntuplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. In Proc. Int. Symp. on Physical Design, pages 236-238, 2005.
7. K. Doll, F. M. Johannes, and K. J. Antreich. Iterative placement improvement by network flow methods. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 13(10):1189-1200, 1994.
8. W. Naylor et al. US patent 6,301,693: Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer, 2001.
9. B. Hu and M. Marek-Sadowska. Multilevel fixed-point-addition-based vlsi placemen. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(8):1188-1203, August 2005.
10. Z.-W. Jiang, T.-C. Chen, T.-C. Hsu, H.-C. Chenz, and Y-W. Chang. Ntuplace2: A hybrid placer using partitioning and analytical techniques. In Proc. Int. Symp. on Physical Design, pages 215-217, 2006.
11. A. B. Kahng, S. Reda, and Q. Wang. Architecture and details of a high quality, large-scale analytical placer. In Proc. Int. Conf. on Computer Aided Design, pages 891-898, 2005.
12. C. Li, C.-K. Koh, and P. H. Madden. Floorplan management: Incremental placement for gate sizing and buffer insertion. In Proc. Asia South Pacific Design Automation Conf, pages 349-354, 2005.
13. C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H. Madden. Routability-driven placement and white space allocation. In Proc. Int. Conf. on Computer Aided Design, pages 394-401, 2004.
14. G.-J. Nam, C. J. Alpert, P. G. Villarubbia, B. Winter, and M. C. Yildiz. The ISPD2005 placement contest and benchmark suite. In Proc. Int. Symp. on Physical Design, pages 216-220, 2005.
15. G.-J. Nam, S. Reda, C. J. Alpert, P. G. Villarubbia, and A. B. Kahng. A fast hierarchical quadratic placement algorithm. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(4):678-691, 2006.
16. B. Obermeier, H. Ranke, and F. M. Johannes. Kraftwerk: a versatile placement approach. In Proc. Int. Symp. on Physical Design, pages 242-244, 2005.
17. M. Pan, N. Viswanathan, and C. C.-N. Chu. An efficient and effective detailed placement algorithm. In Proc. Int. Conf. on Computer Aided Design, pages 48-55, 2005.
18. J. Roy, D. Papa, A. Ng, and I. Markov. Satisfying whitespace requirements in top-down placement. In Proc. Int. Symp. on Physical Design, pages 206-208, 2006.
19. T. Taghavi, X. Yang, B-K Choi, M. Wang, and M. Sarrafzadeh. Dragon2006: blockage-aware congestion-controlling mixed-size placer. In Proc. Int. Symp. on Physical Design, pages 209-211, 2006.
20. N. Viswanathan and C. C.-N. Chu. Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(5):722-733, May 2005.
21. C. Zhu, R. H. Byrd, and J. Nocedal. L-BFGS-B, FORTRAN routiens for large scale bound constrained optimization. ACM Transactions on Mathematical Software, 23(4):550-560, 1997.