Instruction flow-based front-end throttling for power-aware high-performance processors

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 16-21

  Baniasadi, A ^a   Moshovos, A ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW ANALYSIS; DECODING; ENERGY DISSIPATION; PIPELINE PROCESSING SYSTEMS;

INSTRUCTION FLOW; PIPELINE TRAFFIC;

PROGRAM PROCESSORS;

EID: 0034878682     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383088     Document Type: Conference Paper

References (5)

1. A power analysis of a microprocessor: A study of the MIPS R3000 architecture
2. Assigning confidence to conditional branch predictions
3. Pipeline gating: Speculation control for energy reduction
4. Confidence estimation for speculation control
5. Thermal management systems for high performance PowerPC microprocessors