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Volumn 254, Issue 19, 2008, Pages 6168-6173

Silicon-on-Nothing MOSFETs: An efficient solution for parasitic substrate coupling suppression in SOI devices

Author keywords

Output conductance; Silicon on Nothing MOSFETs; SOI MOSFETs; Substrate crosstalk

Indexed keywords

MOSFET DEVICES; SILICON;

EID: 45049084003     PISSN: 01694332     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.apsusc.2008.02.171     Document Type: Article
Times cited : (22)

References (23)
  • 1
    • 0030379801 scopus 로고    scopus 로고
    • Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques
    • Tenbroek B.M., et al. Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques. IEEE Trans. Electron. Dev. 43 (1996) 2240-2248
    • (1996) IEEE Trans. Electron. Dev. , vol.43 , pp. 2240-2248
    • Tenbroek, B.M.1
  • 2
    • 0035310019 scopus 로고    scopus 로고
    • SOI thermal impedance extraction methodology and its significance for circuits simulation
    • Jin W., Liu W., Fung S.K.H., Chan P.C.H., and Hu C. SOI thermal impedance extraction methodology and its significance for circuits simulation. IEEE Trans. Electron. Dev. 48 (2001) 730-735
    • (2001) IEEE Trans. Electron. Dev. , vol.48 , pp. 730-735
    • Jin, W.1    Liu, W.2    Fung, S.K.H.3    Chan, P.C.H.4    Hu, C.5
  • 4
    • 0026904737 scopus 로고
    • A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's
    • Howes R., and Redman-White W. A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's. IEEE J. Solid-State Circuits 27 (1992) 1186-1192
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 1186-1192
    • Howes, R.1    Redman-White, W.2
  • 6
    • 0042592899 scopus 로고    scopus 로고
    • Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs
    • Kilchytska V., Levacq D., Lederer D., Raskin J.P., and Flandre D. Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs. IEEE Electron. Dev. Lett. 24 (2003) 414-417
    • (2003) IEEE Electron. Dev. Lett. , vol.24 , pp. 414-417
    • Kilchytska, V.1    Levacq, D.2    Lederer, D.3    Raskin, J.P.4    Flandre, D.5
  • 10
    • 45049084121 scopus 로고    scopus 로고
    • Substrate-related output conductance frequency response of FD SOI MOSFETs: influence of channel length and substrate temperature
    • Kilchytska V., Pailloncy G., Raskin J.-P., Collaert N., Jurczak M., and Flandre D. Substrate-related output conductance frequency response of FD SOI MOSFETs: influence of channel length and substrate temperature. Proc. ULIS (2007) 71-74
    • (2007) Proc. ULIS , pp. 71-74
    • Kilchytska, V.1    Pailloncy, G.2    Raskin, J.-P.3    Collaert, N.4    Jurczak, M.5    Flandre, D.6
  • 11
    • 0034315445 scopus 로고    scopus 로고
    • Silicon-on-Nothing (SON)-an innovative process for advanced CMOS
    • Jurczak M., et al. Silicon-on-Nothing (SON)-an innovative process for advanced CMOS. IEEE Trans. Electron. Dev. 47 (2000) 2179-2187
    • (2000) IEEE Trans. Electron. Dev. , vol.47 , pp. 2179-2187
    • Jurczak, M.1
  • 12
    • 0036498428 scopus 로고    scopus 로고
    • Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture
    • Ernst T., Tinella C., Raynaud C., and Cristoloveanu S. Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture. Solid State Electron. 46 (2002) 373-378
    • (2002) Solid State Electron. , vol.46 , pp. 373-378
    • Ernst, T.1    Tinella, C.2    Raynaud, C.3    Cristoloveanu, S.4
  • 13
    • 34548537038 scopus 로고    scopus 로고
    • Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity
    • Kilchytska V., Chung T.M., Olbrechts B., Vovk Ya., Raskin J.-P., and Flandre D. Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity. Solid State Electron. 51 (2007) 1238-1244
    • (2007) Solid State Electron. , vol.51 , pp. 1238-1244
    • Kilchytska, V.1    Chung, T.M.2    Olbrechts, B.3    Vovk, Ya.4    Raskin, J.-P.5    Flandre, D.6
  • 14
    • 0001636831 scopus 로고    scopus 로고
    • Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET
    • Koh R. Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET. Jpn. J. Appl. Phys. 38 (1999) 2294-2299
    • (1999) Jpn. J. Appl. Phys. , vol.38 , pp. 2294-2299
    • Koh, R.1
  • 15
    • 17744417117 scopus 로고    scopus 로고
    • SON (Silicon-On-Nothing) MOSFET using ESS (Empty space in silicon) technique for SoC applications
    • Sato T., et al. SON (Silicon-On-Nothing) MOSFET using ESS (Empty space in silicon) technique for SoC applications. IEDM (2001) 809-812
    • (2001) IEDM , pp. 809-812
    • Sato, T.1
  • 16
    • 21644442426 scopus 로고    scopus 로고
    • SON (Silicon-On-Nothing) technological CMOS platform: highly performant devices and SRAM cells
    • Monfray S., Chanemougame D., and Borel S. SON (Silicon-On-Nothing) technological CMOS platform: highly performant devices and SRAM cells. IEDM (2004) 635-638
    • (2004) IEDM , pp. 635-638
    • Monfray, S.1    Chanemougame, D.2    Borel, S.3
  • 18
    • 33846086965 scopus 로고    scopus 로고
    • Silicon-on-Nothing MOSFETs fabricated with hydrogen and helium co-implantation
    • Bu W.-H., et al. Silicon-on-Nothing MOSFETs fabricated with hydrogen and helium co-implantation. Chin. Phys. 15 (2006) 2751-2755
    • (2006) Chin. Phys. , vol.15 , pp. 2751-2755
    • Bu, W.-H.1
  • 19
    • 33847311369 scopus 로고    scopus 로고
    • Planar double-gate SOI MOS devices: fabrication by wafer bonding over pre-patterned cavities and electrical characterization
    • Chung T.M., Olbrechts B., Soderval U., Bengtsson S., Flandre D., and Raskin J.-P. Planar double-gate SOI MOS devices: fabrication by wafer bonding over pre-patterned cavities and electrical characterization. Solid State Electron. 51 (2007) 231-238
    • (2007) Solid State Electron. , vol.51 , pp. 231-238
    • Chung, T.M.1    Olbrechts, B.2    Soderval, U.3    Bengtsson, S.4    Flandre, D.5    Raskin, J.-P.6
  • 20
    • 0035335740 scopus 로고    scopus 로고
    • FD SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
    • Flandre D., et al. FD SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems. Solid State Electron. 45 (2001) 541-549
    • (2001) Solid State Electron. , vol.45 , pp. 541-549
    • Flandre, D.1
  • 21
    • 25844508965 scopus 로고    scopus 로고
    • Investigation of buried insulators with high thermal conductivity in SOI MOSFETs: thermal properties and short channel effects
    • Bresson N., Cristoloveanu S., Mazuré C., Letertre F., and Iwai H. Investigation of buried insulators with high thermal conductivity in SOI MOSFETs: thermal properties and short channel effects. Solid State Electron. 49 (2005) 1522-1528
    • (2005) Solid State Electron. , vol.49 , pp. 1522-1528
    • Bresson, N.1    Cristoloveanu, S.2    Mazuré, C.3    Letertre, F.4    Iwai, H.5
  • 22
    • 0030127650 scopus 로고    scopus 로고
    • Modeling and application of fully-depleted SOI MOSFETs for low-voltage low-power analog CMOS circuits
    • Flandre D., Ferreira L., Jespers P.G.A., and Colinge J.-P. Modeling and application of fully-depleted SOI MOSFETs for low-voltage low-power analog CMOS circuits. Solid-State Electron. 39 (1996) 455-460
    • (1996) Solid-State Electron. , vol.39 , pp. 455-460
    • Flandre, D.1    Ferreira, L.2    Jespers, P.G.A.3    Colinge, J.-P.4
  • 23
    • 0037560969 scopus 로고    scopus 로고
    • Influence of device engineering on the analog and RF performance of SOI MOSFETs
    • Kilchytska V., et al. Influence of device engineering on the analog and RF performance of SOI MOSFETs. IEEE Trans. Electron. Dev. 50 (2003) 577-588
    • (2003) IEEE Trans. Electron. Dev. , vol.50 , pp. 577-588
    • Kilchytska, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.