-
1
-
-
0032625315
-
Analytical threshold voltage model for ultrathin SOI MOSFET's including short-channel and floating-body effects
-
Adan A O, Higashi K and Fukushima Y 1999 Analytical threshold voltage model for ultrathin SOI MOSFET's including short-channel and floating-body effects IEEE Trans. Electron Devices 46 729-37
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 729-737
-
-
Adan, A.O.1
Higashi, K.2
Fukushima, Y.3
-
2
-
-
0001636831
-
Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET
-
Kon R 1999 Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET Japan. J. Appl. Phys. 38 2294-9
-
(1999)
Japan. J. Appl. Phys.
, vol.38
, pp. 2294-2299
-
-
Kon, R.1
-
3
-
-
0036927506
-
Experimental study on carrier transport mechanism in ultrathin-body SOI n- And p-MOSFETs with SOI thickness less than 5 nm
-
Uchida K, Watanabe H, Kinoshita A, Koga J, Numata T and Takagi S-i 2002 Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm IEDM Tech. Dig. 2002, pp 47-50
-
(2002)
IEDM Tech. Dig. 2002
, pp. 47-50
-
-
Uchida, K.1
Watanabe, H.2
Kinoshita, A.3
Koga, J.4
Numata, T.5
Takagi, S.-I.6
-
4
-
-
0036923566
-
SON (silicon-on-nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5 nm-thick Si-films: The simplest way to integration of metal gates on thin FD channels
-
Monfray S et al 2002 SON (silicon-on-nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels IEDM Tech. Dig. 2002, pp 263-6
-
(2002)
IEDM Tech. Dig. 2002
, pp. 263-266
-
-
Monfray, S.1
-
5
-
-
19944420951
-
Highly performant double gate MOSFET realized with SON process
-
Harrison S et al 2003 Highly performant double gate MOSFET realized with SON process IEDM Tech. Dig. 2002, pp 18.6.1-18.6.4
-
(2003)
IEDM Tech. Dig. 2002
-
-
Harrison, S.1
-
6
-
-
0442326807
-
Silicon-on-nothing MOSFETs: Performance, short-channel effects, and backgate coupling
-
Pretet J, Monfray S, Cristoloveanu S and Skotnicki T 2004 Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling IEEE Trans. Electron Devices 51 240-4
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, pp. 240-244
-
-
Pretet, J.1
Monfray, S.2
Cristoloveanu, S.3
Skotnicki, T.4
-
7
-
-
0034315445
-
Silicon-on-nothing (SON) - An innovative process for advanced CMOS
-
Jurczak M et al 2000 Silicon-on-nothing (SON) - an innovative process for advanced CMOS IEEE Trans. Electron Devices 47 2179-85
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 2179-2185
-
-
Jurczak, M.1
-
8
-
-
17744417117
-
SON (silicon on nothing) MOSFET using ESS (empty space in silicon) technique for SoC applications
-
Sato T et al 2001 SON (silicon on nothing) MOSFET using ESS (empty space in silicon) technique for SoC applications IEDM Tech. Dig. 2002, pp 809-12
-
(2001)
IEDM Tech. Dig. 2002
, pp. 809-812
-
-
Sato, T.1
-
10
-
-
0035717576
-
First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance
-
Monfray S et al 2001 First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance IEDM Tech. Dig. 2002, pp 645-8
-
(2001)
IEDM Tech. Dig. 2002
, pp. 645-648
-
-
Monfray, S.1
-
11
-
-
0142154781
-
Strain evaluation for thin strained-Si on SGOI and strained-Si on nothing (SSON) structures using nano-beam electron diffraction (NBD)
-
Usuda K, Numata T, Tezuka T, Sugiyama N, Moriyama Y, Nakaharai S and Takagi S 2003 Strain evaluation for thin strained-Si on SGOI and strained-Si on nothing (SSON) structures using nano-beam electron diffraction (NBD) Proc. IEEE Int. SOI Conf. pp 138-9
-
(2003)
Proc. IEEE Int. SOI Conf.
, pp. 138-139
-
-
Usuda, K.1
Numata, T.2
Tezuka, T.3
Sugiyama, N.4
Moriyama, Y.5
Nakaharai, S.6
Takagi, S.7
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