메뉴 건너뛰기




Volumn 51, Issue 9, 2007, Pages 1238-1244

Electrical characterization of true Silicon-On-Nothing MOSFETs fabricated by Si layer transfer over a pre-etched cavity

Author keywords

Frequency response; Output conductance; Self heating effect; Si layer transfer; Silicon On Nothing MOSFETs; Ultra thin BOX

Indexed keywords

ELECTRIC PROPERTIES; METALLIC FILMS; SILICON; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; SUBSTRATES;

EID: 34548537038     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.07.021     Document Type: Article
Times cited : (36)

References (19)
  • 1
    • 0001636831 scopus 로고    scopus 로고
    • Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET
    • Koh R. Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET. Jpn J Appl Phys 38 (1999) 2294-2299
    • (1999) Jpn J Appl Phys , vol.38 , pp. 2294-2299
    • Koh, R.1
  • 2
    • 0034315445 scopus 로고    scopus 로고
    • Silicon-on-nothing (SON) - an innovative process for advanced CMOS
    • Jurczak M., Skotnicki T., Paoli M., et al. Silicon-on-nothing (SON) - an innovative process for advanced CMOS. IEEE Trans Electron Dev 47 (2000) 2179-2187
    • (2000) IEEE Trans Electron Dev , vol.47 , pp. 2179-2187
    • Jurczak, M.1    Skotnicki, T.2    Paoli, M.3
  • 3
    • 0035717576 scopus 로고    scopus 로고
    • First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance
    • Monfray S., Skotnicki T., Morand Y., et al. First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance. IEDM (2001) 645-648
    • (2001) IEDM , pp. 645-648
    • Monfray, S.1    Skotnicki, T.2    Morand, Y.3
  • 4
    • 17744417117 scopus 로고    scopus 로고
    • SON (silicon on nothing) MOSFET using ESS (empty space in silicon) technique for SoC applications
    • Sato T., Nii H., Hatano M., et al. SON (silicon on nothing) MOSFET using ESS (empty space in silicon) technique for SoC applications. IEDM (2001) 809-812
    • (2001) IEDM , pp. 809-812
    • Sato, T.1    Nii, H.2    Hatano, M.3
  • 5
    • 21644442426 scopus 로고    scopus 로고
    • SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells
    • Monfray S., Chanemougame D., and Borel S. SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells. IEDM (2004) 635-638
    • (2004) IEDM , pp. 635-638
    • Monfray, S.1    Chanemougame, D.2    Borel, S.3
  • 6
    • 13644275694 scopus 로고    scopus 로고
    • Scaling capability improvement of silicon-on-void (SOV) MOSFET
    • Tian Y., Bu W., Wu D., An X., Huang R., and Wang Y. Scaling capability improvement of silicon-on-void (SOV) MOSFET. Semicond Sci Technol 20 (2005) 1-5
    • (2005) Semicond Sci Technol , vol.20 , pp. 1-5
    • Tian, Y.1    Bu, W.2    Wu, D.3    An, X.4    Huang, R.5    Wang, Y.6
  • 7
    • 33846086965 scopus 로고    scopus 로고
    • Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation
    • Bu W.-H., Huang R., Li M., et al. Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation. Chin Phys 15 (2006) 2751-2755
    • (2006) Chin Phys , vol.15 , pp. 2751-2755
    • Bu, W.-H.1    Huang, R.2    Li, M.3
  • 8
    • 0000990003 scopus 로고    scopus 로고
    • Empty-space-in-silicon technique for fabricating a silicon-on-nothing structure
    • Mizushima I., Sato T., Taniguchi S., and Tsunashima Y. Empty-space-in-silicon technique for fabricating a silicon-on-nothing structure. Appl Phys Lett 77 (2000) 3290-3292
    • (2000) Appl Phys Lett , vol.77 , pp. 3290-3292
    • Mizushima, I.1    Sato, T.2    Taniguchi, S.3    Tsunashima, Y.4
  • 9
    • 33847311369 scopus 로고    scopus 로고
    • Planar double-gate SOI MOS devices: fabrication by wafer bonding over pre-patterned cavities and electrical characterization
    • Chung T.M., Olbrechts B., Soderval U., Bengtsson S., Flandre D., and Raskin J.-P. Planar double-gate SOI MOS devices: fabrication by wafer bonding over pre-patterned cavities and electrical characterization. Solid State Electron 51 (2007) 231-238
    • (2007) Solid State Electron , vol.51 , pp. 231-238
    • Chung, T.M.1    Olbrechts, B.2    Soderval, U.3    Bengtsson, S.4    Flandre, D.5    Raskin, J.-P.6
  • 10
    • 0042592899 scopus 로고    scopus 로고
    • Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs
    • Kilchytska V., Levacq D., Lederer D., Raskin J.P., and Flandre D. Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs. IEEE Electron Dev Lett 24 (2003) 414-417
    • (2003) IEEE Electron Dev Lett , vol.24 , pp. 414-417
    • Kilchytska, V.1    Levacq, D.2    Lederer, D.3    Raskin, J.P.4    Flandre, D.5
  • 11
    • 34247615579 scopus 로고    scopus 로고
    • Frequency variation of the small signal output conductance of decananometer MOSFET due to substrate crosstalk
    • Kilchytska V., Pailloncy G., Lederer D., Raskin J.P., Collaert N., Jurczak M., et al. Frequency variation of the small signal output conductance of decananometer MOSFET due to substrate crosstalk. IEEE Electron Dev Lett 28 (2007) 419-421
    • (2007) IEEE Electron Dev Lett , vol.28 , pp. 419-421
    • Kilchytska, V.1    Pailloncy, G.2    Lederer, D.3    Raskin, J.P.4    Collaert, N.5    Jurczak, M.6
  • 12
    • 0035335740 scopus 로고    scopus 로고
    • Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
    • Flandre D., Adriaensen S., Akheyar A., et al. Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems. Solid State Electron 45 (2001) 541-549
    • (2001) Solid State Electron , vol.45 , pp. 541-549
    • Flandre, D.1    Adriaensen, S.2    Akheyar, A.3
  • 13
    • 25844508965 scopus 로고    scopus 로고
    • Investigation of buried insulators with high thermal conductivity in SOI MOSFETs: thermal properties and short channel effects
    • Bresson N., Cristoloveanu S., Mazuré C., Letertre F., and Iwai H. Investigation of buried insulators with high thermal conductivity in SOI MOSFETs: thermal properties and short channel effects. Solid State Electron 49 (2005) 1522-1528
    • (2005) Solid State Electron , vol.49 , pp. 1522-1528
    • Bresson, N.1    Cristoloveanu, S.2    Mazuré, C.3    Letertre, F.4    Iwai, H.5
  • 14
    • 0030127650 scopus 로고    scopus 로고
    • Modeling and application of fully-depleted SOI MOSFETs for low-voltage low-power analog CMOS circuits
    • Flandre D., Ferreira L., Jespers P.G.A., and Colinge J.-P. Modeling and application of fully-depleted SOI MOSFETs for low-voltage low-power analog CMOS circuits. Solid State Electron 39 (1996) 455-460
    • (1996) Solid State Electron , vol.39 , pp. 455-460
    • Flandre, D.1    Ferreira, L.2    Jespers, P.G.A.3    Colinge, J.-P.4
  • 16
    • 0030379801 scopus 로고    scopus 로고
    • Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques
    • Tenbroek B.M., Lee M.S.L., Redman-White W., et al. Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques. IEEE Trans Electron Dev 43 (1996) 2240-2248
    • (1996) IEEE Trans Electron Dev , vol.43 , pp. 2240-2248
    • Tenbroek, B.M.1    Lee, M.S.L.2    Redman-White, W.3
  • 17
    • 0035310019 scopus 로고    scopus 로고
    • SOI thermal impedance extraction methodology and its significance for circuits simulation
    • Jin W., Liu W., Fung S.K.H., Chan P.C.H., and Hu C. SOI thermal impedance extraction methodology and its significance for circuits simulation. IEEE Trans Electron Dev 48 (2001) 730-735
    • (2001) IEEE Trans Electron Dev , vol.48 , pp. 730-735
    • Jin, W.1    Liu, W.2    Fung, S.K.H.3    Chan, P.C.H.4    Hu, C.5
  • 18
    • 0036498428 scopus 로고    scopus 로고
    • Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture
    • Ernst T., Tinella C., Raynaud C., and Cristoloveanu S. Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture. Solid State Electron 46 (2002) 373-378
    • (2002) Solid State Electron , vol.46 , pp. 373-378
    • Ernst, T.1    Tinella, C.2    Raynaud, C.3    Cristoloveanu, S.4
  • 19
    • 0442326807 scopus 로고    scopus 로고
    • Silicon-on-nothing MOSFETs: performance, short-channel effects and backgate coupling
    • Pretet J., Monfray S., Cristoloveanu S., and Skotnicki T. Silicon-on-nothing MOSFETs: performance, short-channel effects and backgate coupling. IEEE Trans Electron Dev 51 (2004) 240-245
    • (2004) IEEE Trans Electron Dev , vol.51 , pp. 240-245
    • Pretet, J.1    Monfray, S.2    Cristoloveanu, S.3    Skotnicki, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.