FPGA-based fault injection into switch-level models

Microprocessors and Microsystems

Volumn 28, Issue 5-6 SPEC. ISS., 2004, Pages 317-327

  Ejlali, Alireza ^a   Miremadi, Seyed Ghassem ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

FPGA; Gate level modeling; Speed up; Switch level modeling

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; SWITCHES;

FAULT INJECTION; GATE-LEVEL MODELING; SPEED-UP; SWITCH-LEVEL MODELING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2642511652     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2004.03.007     Document Type: Article

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