Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 250-258

  Civera, P ^a   Macchiarulo, L ^a   Rebaudengo, M ^a   Sonza Reorda, M ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; USER INTERFACES;

FAULT INJECTION CAMPAIGN; SPEED UP FIGURE;

VLSI CIRCUITS;

EID: 0035193910     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Time redundancy based soft-error tolerance to rescue nanometer technologies
2. Experimental analysis of computer system dependability
3. Sequential circuit fault simulation using logic emulation
4. Fault emulation: A new methodology for fault grading
5. Using run-time reconfiguration for fault injection in hardware prototypes
6. Fault injection in VHDL descriptions and emulation
7. A gate-level simulation environment for alpha-particle-induced transient faults
8. New techniques for accelerating fault injection in VHDL descriptions
9. Fault-list collapsing for fault injection experiments
10. RT-level ITC 99 benchmarks and first ATPG results