-
1
-
-
0038721289
-
Basic mechanisms and modeling of single-event upset in digital microelectronics
-
June
-
P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, pp. 583-602, June 2003.
-
(2003)
IEEE Trans. Nucl. Sci.
, vol.50
, pp. 583-602
-
-
Dodd, P.E.1
Massengill, L.W.2
-
2
-
-
0031373956
-
Attenutation of single event inducet pulses in CMOS combinational logic
-
Dec.
-
M. P. Baze and S. P. Buchner, "Attenutation of single event inducet pulses in CMOS combinational logic," IEEE Trans. Nucl. Sci., vol. 44, pp. 2217-2223, Dec. 1997.
-
(1997)
IEEE Trans. Nucl. Sci.
, vol.44
, pp. 2217-2223
-
-
Baze, M.P.1
Buchner, S.P.2
-
3
-
-
0031367158
-
Comparison of error rates in combinational and sequential logic
-
Dec.
-
S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger, "Comparison of error rates in combinational and sequential logic," IEEE Trans. Nucl. Sci., vol. 44, pp. 2209-2216, Dec. 1997.
-
(1997)
IEEE Trans. Nucl. Sci.
, vol.44
, pp. 2209-2216
-
-
Buchner, S.1
Baze, M.2
Brown, D.3
McMorrow, D.4
Melinger, J.5
-
5
-
-
0031123369
-
Fault injection techniques and tools
-
Apr.
-
M.-C. Hsueh, T. K. Tsai, and R. K. Iyer, "Fault injection techniques and tools," IEEE Trans. Comput., vol. 30, pp. 75-82, Apr. 1997.
-
(1997)
IEEE Trans. Comput.
, vol.30
, pp. 75-82
-
-
Hsueh, M.-C.1
Tsai, T.K.2
Iyer, R.K.3
-
6
-
-
0028994255
-
A switch-level algorithm for simulation of transients in combination logic
-
P. Dahlgren and P. Liden, "A switch-level algorithm for simulation of transients in combination logic," in Proc. IEEE Fault Tolerant Computing Symp., 1995, pp. 207-216.
-
(1995)
Proc. IEEE Fault Tolerant Computing Symp.
, pp. 207-216
-
-
Dahlgren, P.1
Liden, P.2
-
7
-
-
0026400768
-
Simulation of SEU transients in CMOS ICs
-
Dec.
-
N. Kaul, B. L. Bhuva, and S. E. Kerns, "Simulation of SEU transients in CMOS ICs," IEEE Trans. Nucl. Sci., vol. 38, pp. 1514-1520, Dec. 1991.
-
(1991)
IEEE Trans. Nucl. Sci.
, vol.38
, pp. 1514-1520
-
-
Kaul, N.1
Bhuva, B.L.2
Kerns, S.E.3
-
8
-
-
0028018774
-
Fault injection into VHDL models: The MEFISTO tool
-
E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, "Fault injection into VHDL models: the MEFISTO tool," in Proc. IEEE Fault Tolerant Computing Symp., 1994, pp. 66-75.
-
(1994)
Proc. IEEE Fault Tolerant Computing Symp.
, pp. 66-75
-
-
Jenn, E.1
Arlat, J.2
Rimen, M.3
Ohlsson, J.4
Karlsson, J.5
-
9
-
-
27544444307
-
MEFISTO-L: A VHDL-based fault injection tool for the experimental assessment of fault tolerance
-
J. Boué, P. Pétillon, and Y. Crouzet, "MEFISTO-L: a VHDL-based fault injection tool for the experimental assessment of fault tolerance," in Proc. IEEE Fault-Tolerant Computing Symp., 1998, pp. 168-173.
-
(1998)
Proc. IEEE Fault-tolerant Computing Symp.
, pp. 168-173
-
-
Boué, J.1
Pétillon, P.2
Crouzet, Y.3
-
10
-
-
0035722241
-
Exploiting circuit emulation for fast hardness evaluation
-
Dec.
-
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and M. Violante. "Exploiting circuit emulation for fast hardness evaluation, " IEEE Trans. Nucl. Sci., vol. 48, pp. 2210-2216, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci.
, vol.48
, pp. 2210-2216
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, M.5
-
11
-
-
0034501974
-
Using run-time reconfiguration for fault injection in hardware prototypes
-
L. Antoni, R. Leveugle, and B. Fehér, "Using run-time reconfiguration for fault injection in hardware prototypes," in Proc. IEEE Symp. Defect and Fault Tolerance in VLSI Systems, 2000, pp. 405-413.
-
(2000)
Proc. IEEE Symp. Defect and Fault Tolerance in VLSI Systems
, pp. 405-413
-
-
Antoni, L.1
Leveugle, R.2
Fehér, B.3
-
12
-
-
0034452351
-
Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor
-
Dec.
-
L. W. Massengill, A. E. Baranski, D. O. Van Nort, J. Meng, and B. L. Bhuva, "Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor," IEEE Trans. Nucl. Sci., vol. 47, pp. 2609-2615, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci.
, vol.47
, pp. 2609-2615
-
-
Massengill, L.W.1
Baranski, A.E.2
Van Nort, D.O.3
Meng, J.4
Bhuva, B.L.5
-
13
-
-
84893748923
-
New techniques for speeding-up fault-injection campaigns
-
L. Berrojo, I. González, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, and C. Lopez, "New techniques for speeding-up fault-injection campaigns," in Proc. IEEE Design, Automation and Test in Europe, 2002, pp. 847-852.
-
(2002)
Proc. IEEE Design, Automation and Test in Europe
, pp. 847-852
-
-
Berrojo, L.1
González, I.2
Corno, F.3
Sonza Reorda, M.4
Squillero, G.5
Entrena, L.6
Lopez, C.7
-
16
-
-
0030646135
-
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model
-
S. Manich and J. Figueras, "Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model," in Proc. IEEE European Design and Test Conf., 1997, pp. 597-602.
-
(1997)
Proc. IEEE European Design and Test Conf.
, pp. 597-602
-
-
Manich, S.1
Figueras, J.2
-
17
-
-
1242264201
-
-
[Online]
-
www.gaisler.com [Online]
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