Exploiting circuit emulation for fast hardness evaluation

IEEE Transactions on Nuclear Science

Volumn 48, Issue 6 I, 2001, Pages 2210-2216

  Civera, P ^a   Macchiarulo, L ^a   Rebaudengo, M ^a   Sonza Reorda, M ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Fault injection; FPGA; Safety critical applications; Single event upset (SEU)

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC FAULT LOCATION; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT TESTING;

FAULT INJECTION; SINGLE-EVENT UPSET (SEU);

VLSI CIRCUITS;

EID: 0035722241     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.983197     Document Type: Conference Paper

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