Using run-time reconfiguration for fault injection applications

IEEE Transactions on Instrumentation and Measurement

Volumn 52, Issue 5, 2003, Pages 1468-1473

  Antoni, Lörinc ^a,b   Leveugle, Régis ^a   Fehér, Béla ^b  

^a TIMA LABORATORY   (France)

^b BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

Author keywords

Fault injection; FPGA; Hardware prototyping; Partial run time reconfiguration (RTR)

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; JAVA PROGRAMMING LANGUAGE; RAPID PROTOTYPING;

FAULT INJECTION; HARDWARE PROTOTYPING; PARTIAL RUN-TIME RECONFIGURATION;

INTEGRATED CIRCUIT TESTING;

EID: 0242468176     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2003.817144     Document Type: Article

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