On combining fault classification and error propagation analysis in RT-level dependability evaluation

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 227-232

  Amman, A ^a   Hadjiat, K ^a   Leveugle, R ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ERROR CORRECTION; MATHEMATICAL MODELS; MICROCONTROLLERS; PRODUCT DESIGN;

ERROR PROPAGATION ANALYSIS (EPA); FAULT CLASSIFICATIONS; FINITE IMPULSE RESPONSE (FIR); SPECIAL FUNCTION REGISTERS (SFR);

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 10444233479     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A. Ammari, R. Leveugle, M. Sonza-Reorda, M. Violante, "Detailed comparison of dependability analyses performed at RT and gate levels", Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA, USA, November 3-5, 2003, pp. 336-343
2. R. Leveugle, K. Hadjiat, "Multi-level fault injections in VHDL descriptions: alternative approaches and experiments", Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer, vol. 19, no. 5, October 2003, pp. 559-575
3. E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson, "Fault injection into VHDL models: the MEFISTO tool", 24th Symposium on Fault-Tolerant Computing (FTCS), 1994, pp. 66-75
4. G. C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco, "Bit-flip injection in processor-based architectures: a case study", 8th IEEE International On-Line Testing workshop, Isle of Bendor, France, July 8-10, 2002, pp. 117-127
5. R. Leveugle, "Fault injection in VHDL descriptions and emulation", Proc. IEEE. Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, October 25-27, 2000, pp. 414-419
6. P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, A. Violante, "Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits", "The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, October 24-26, 2001", IEEE Computer Society Press, Los Alamitos, California, 2001, pp. 250-258
7. http://www.8051.free.fr/