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Volumn 49 I, Issue 6, 2002, Pages 3156-3162

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Author keywords

Extraterrestrial radiation effects; Fault injection; Heavy ion testing; Integrated circuit radiation effects; Integrated circuit testing; Ion radiation effects; Microprocessor testing; PowerPC7400; Processor errors; Radiation effects

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; HEAVY IONS; INTEGRATED CIRCUITS; RADIATION EFFECTS;

EID: 0036952552     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2002.805982     Document Type: Conference Paper
Times cited : (11)

References (8)
  • 1
    • 0002229004 scopus 로고    scopus 로고
    • Commercial processor single event tests
    • F. Bezerra et al., "Commercial processor single event tests," RADECS Conf. Data Workshop Rec., pp. 41-46, 1997.
    • (1997) RADECS Conf. Data Workshop Rec. , pp. 41-46
    • Bezerra, F.1
  • 2
    • 0032002385 scopus 로고
    • Xception: A technique for the experimental evaluation of dependability in modern computers
    • Feb.
    • J. Carreira, H. Madeira, and J. G. Silva, "Xception: A technique for the experimental evaluation of dependability in modern computers," IEEE Trans. Software Eng., vol. 24, pp. 125-136, Feb. 1988.
    • (1988) IEEE Trans. Software Eng. , vol.24 , pp. 125-136
    • Carreira, J.1    Madeira, H.2    Silva, J.G.3
  • 4
    • 0034450666 scopus 로고    scopus 로고
    • Predicting error rate for microprocessor-based digital architectures through C.E.U. (code emulating upsets) injection
    • Dec.
    • R. Velazco, S. Rezgui, and R. Ecoffet, "Predicting error rate for microprocessor-based digital architectures through C.E.U. (code emulating upsets) injection," IEEE Trans. Nucl. Sci., vol. 47, pp. 2405-2411, Dec. 2000.
    • (2000) IEEE Trans. Nucl. Sci. , vol.47 , pp. 2405-2411
    • Velazco, R.1    Rezgui, S.2    Ecoffet, R.3
  • 7
    • 0002852824 scopus 로고    scopus 로고
    • THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment
    • Sitges, Spain, May
    • R. Velazco, P. Cheynet, A. Bofill, and R. Ecoffet, "THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment," in IEEE Eur. Test Workshop (ETW'98), Sitges, Spain, May 1998, pp. 89-90.
    • (1998) IEEE Eur. Test Workshop (ETW'98) , pp. 89-90
    • Velazco, R.1    Cheynet, P.2    Bofill, A.3    Ecoffet, R.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.