-
1
-
-
0032284102
-
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation
-
H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation," in IEDM Tech. Dig., 1998, pp. 407-410.
-
(1998)
IEDM Tech. Dig
, pp. 407-410
-
-
Wong, H.-S.P.1
Frank, D.J.2
Solomon, P.M.3
-
3
-
-
0034453428
-
Gate length scaling and threshold voltage control of double-gate MOSFETs
-
L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," in IEDM Tech. Dig., 2000, pp. 719-722.
-
(2000)
IEDM Tech. Dig
, pp. 719-722
-
-
Chang, L.1
Tang, S.2
King, T.-J.3
Bokor, J.4
Hu, C.5
-
4
-
-
0032255808
-
A folded-channel MOSFET for deep-sub-tenth micron era
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, "A folded-channel MOSFET for deep-sub-tenth micron era," in IEDM Tech. Dig., 1998, pp. 1032-1034.
-
(1998)
IEDM Tech. Dig
, pp. 1032-1034
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Anderson, E.4
Takeuchi, H.5
Asano, K.6
King, T.-J.7
Bokor, J.8
Hu, C.9
-
5
-
-
0033329310
-
Sub 50-nm FinFET: PMOS
-
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS," in IEDM Tech. Dig. 1999, pp. 67-70.
-
(1999)
IEDM Tech. Dig
, pp. 67-70
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
Subramanian, V.11
King, T.-J.12
Bokor, J.13
Hu, C.14
-
6
-
-
26244452166
-
Bulk inversion in FinFETs and implied insights on effective gate width
-
Sep
-
S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk inversion in FinFETs and implied insights on effective gate width," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993-1997, Sep. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.9
, pp. 1993-1997
-
-
Kim, S.-H.1
Fossum, J.G.2
Trivedi, V.P.3
-
7
-
-
33645740422
-
Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation
-
Apr
-
D. S. Havalpar, G. Katti, N. DasGupta, and A. DasGupta, "Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 737-742, Apr. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.4
, pp. 737-742
-
-
Havalpar, D.S.1
Katti, G.2
DasGupta, N.3
DasGupta, A.4
-
8
-
-
29044440093
-
FinFET - A self-aligned double-gate MOSFET scalable to 20 nm
-
Dec
-
D. Hisamoto et al., "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
-
9
-
-
20144387099
-
CMOS vertical multiple independent gate field effect transistor-MIGFET
-
Oct
-
L. Mathew et al., "CMOS vertical multiple independent gate field effect transistor-MIGFET," in Proc. IEEE Int. SOI Conf., Oct. 2004, pp. 187-189.
-
(2004)
Proc. IEEE Int. SOI Conf
, pp. 187-189
-
-
Mathew, L.1
-
10
-
-
1942520273
-
High-performance p-type independent-gate FinFETs
-
Apr
-
D. M. Fried, J. S. Duster, and K. T. Kronegay, "High-performance p-type independent-gate FinFETs," IEEE Electron Device Lett., vol. 25, no. 4, pp. 199-201, Apr. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.4
, pp. 199-201
-
-
Fried, D.M.1
Duster, J.S.2
Kronegay, K.T.3
-
11
-
-
21644436369
-
Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application
-
Dec
-
E.-J. Yoon et al., "Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application," in IEDM Tech. Dig., Dec. 2004, pp. 627-630.
-
(2004)
IEDM Tech. Dig
, pp. 627-630
-
-
Yoon, E.-J.1
-
12
-
-
0034860289
-
A sub 40-nm body thickness n-type FinFET
-
Jun
-
D. M. Fried, "A sub 40-nm body thickness n-type FinFET," in Proc. Device Res. Conf., Jun. 2001, pp. 24-25.
-
(2001)
Proc. Device Res. Conf
, pp. 24-25
-
-
Fried, D.M.1
-
13
-
-
19944418823
-
Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode
-
Jun
-
T. Rudenko, N. Collaert, S. De Gendt, V. Kilchytska, M. Jurczak, and D. Flandre, "Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode," Microelectron. Eng., vol. 80, pp. 386-389, Jun. 2005.
-
(2005)
Microelectron. Eng
, vol.80
, pp. 386-389
-
-
Rudenko, T.1
Collaert, N.2
De Gendt, S.3
Kilchytska, V.4
Jurczak, M.5
Flandre, D.6
-
14
-
-
27144463712
-
Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: Suppression of the influence of floating-body effects
-
Oct
-
V. Kilchytska, D. Lederer, N. Collaert, J. P. Raskin, and D. Flandre, "Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: Suppression of the influence of floating-body effects," IEEE Electron Device Lett., vol. 26, no. 10, pp. 749-751, Oct. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.10
, pp. 749-751
-
-
Kilchytska, V.1
Lederer, D.2
Collaert, N.3
Raskin, J.P.4
Flandre, D.5
-
15
-
-
25844498484
-
FinFET analogue characterization from DC to 110 GHz
-
Sep
-
D. Lederer, V. Kilchytska, T. Rudenko, N. Collaert, D. Flandre, A. Dixit, K. De Meyer, and J. P. Raskin, "FinFET analogue characterization from DC to 110 GHz," Solid State Electron., vol. 49, no. 9, pp. 1488-1496, Sep. 2005.
-
(2005)
Solid State Electron
, vol.49
, Issue.9
, pp. 1488-1496
-
-
Lederer, D.1
Kilchytska, V.2
Rudenko, T.3
Collaert, N.4
Flandre, D.5
Dixit, A.6
De Meyer, K.7
Raskin, J.P.8
-
16
-
-
33646023723
-
Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization
-
May
-
J. P. Raskin, T. M. Chung, V. Kilchytska, D. Lederer, and D. Flandre, "Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1088-1095, May 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.5
, pp. 1088-1095
-
-
Raskin, J.P.1
Chung, T.M.2
Kilchytska, V.3
Lederer, D.4
Flandre, D.5
-
17
-
-
0036923438
-
FinFET scaling to 10 nm gate length
-
Dec
-
B. Yu, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig. Dec. 2002, pp. 251-254.
-
(2002)
IEDM Tech. Dig
, pp. 251-254
-
-
Yu, B.1
-
18
-
-
0036923636
-
A functional FinFET-DGCMOS SRAM cell
-
Dec
-
E. Nowak, "A functional FinFET-DGCMOS SRAM cell," in IEDM Tech. Dig., Dec. 2002, pp. 411-414.
-
(2002)
IEDM Tech. Dig
, pp. 411-414
-
-
Nowak, E.1
-
19
-
-
0036684706
-
FinFET design considerations based on 3-D simulation and analytical modeling
-
Aug
-
G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C.-C. Kan, "FinFET design considerations based on 3-D simulation and analytical modeling," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.8
, pp. 1411-1419
-
-
Pei, G.1
Kedzierski, J.2
Oldiges, P.3
Ieong, M.4
Kan, E.C.-C.5
-
20
-
-
0029379215
-
Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology
-
Sep
-
P. C. Yeh and J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1605-1613, Sep. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, Issue.9
, pp. 1605-1613
-
-
Yeh, P.C.1
Fossum, J.G.2
-
21
-
-
0028545015
-
Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's
-
Nov
-
Y. Tosaka, K. Suzuki, and T. Sugii, "Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's," IEEE Electron Device Lett., vol. 15, no. 11, pp. 466-468, Nov. 1994.
-
(1994)
IEEE Electron Device Lett
, vol.15
, Issue.11
, pp. 466-468
-
-
Tosaka, Y.1
Suzuki, K.2
Sugii, T.3
-
22
-
-
0023421993
-
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
-
Sep
-
F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., vol. ED-8, no. 9, pp. 410-412, Sep. 1987.
-
(1987)
IEEE Electron Device Lett
, vol.ED-8
, Issue.9
, pp. 410-412
-
-
Balestra, F.1
Cristoloveanu, S.2
Benachir, M.3
Brini, J.4
Elewa, T.5
-
23
-
-
0041525428
-
A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs
-
Jul
-
Q. Chen, E. M. Harrell II, and J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1631-1637, Jul. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.7
, pp. 1631-1637
-
-
Chen, Q.1
Harrell II, E.M.2
Meindl, J.D.3
-
24
-
-
0027239315
-
Threshold voltage model and subthreshold regime of operation of short-channel MOSFET's
-
Jan
-
T. A. Fjeldly and M. Shur, "Threshold voltage model and subthreshold regime of operation of short-channel MOSFET's," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 137-145, Jan. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, Issue.1
, pp. 137-145
-
-
Fjeldly, T.A.1
Shur, M.2
-
25
-
-
33744925387
-
Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET
-
May
-
H. Abd-Elhamid, B. Iñiguez, D. Jiménez, J. Roig, J. Pallarès, and L. F. Marsal, "Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET," Solid State Electron., vol. 50, no. 5, pp. 805-812, May 2006.
-
(2006)
Solid State Electron
, vol.50
, Issue.5
, pp. 805-812
-
-
Abd-Elhamid, H.1
Iñiguez, B.2
Jiménez, D.3
Roig, J.4
Pallarès, J.5
Marsal, L.F.6
-
26
-
-
41749089004
-
-
Available
-
[Online]. Available: http://mathworld.wolfram.com/ SeparationofVariables.html
-
-
-
-
27
-
-
33947675796
-
Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate all around MOSFETs
-
Mar
-
H. Abd-Elhamid, B. Iñiguez, and J. Roig, "Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate all around MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 3, pp. 572-579, Mar. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.52
, Issue.3
, pp. 572-579
-
-
Abd-Elhamid, H.1
Iñiguez, B.2
Roig, J.3
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