Bulk inversion in FinFETs and implied insights on effective gate width

IEEE Transactions on Electron Devices

Volumn 52, Issue 9, 2005, Pages 1993-1997

  Kim, Seung Hwan ^a   Fossum, Jerry G ^a   Trivedi, Vishal P ^b  

^a University of Florida   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Bulk inversion; Gate layout area; Multi gate MOSFETs

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC DEVICES; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS;

BULK INVERSION; DOUBLE-GATE (DG) TRANSISTOR; GATE LAYOUT AREA; GATE WIDTH; SHORT-CHANNEL EFFECTS (SCES); TRIPLE-GATE (TG) TRANSISTOR;

MOSFET DEVICES;

EID: 26244452166     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.854286     Document Type: Article

References (16)

1. J. G. Fossum, L.-Q. Wang, J.-W. Yang, S.-H. Kim, and V. P. Trivedi, "Pragmatic design of nanoscale multi-gate CMOS," in IEDM Tech Dig., 2004, pp. 613-616.
2. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistors," IEEE Electon Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003.
3. J. G. Fossum, J.-W. Yang, and V. P. Trivedi, "Suppression of corner effects in triple-gate MOSFETs," IEEE Electron Device Lett., vol. 24, no. 12, pp. 745-747, Dec. 2003.
4. V. P. Trivedi and J. G. Fossum, "Scaling fully depleted SOI CMOS," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2095-2103, Oct. 2003.
5. J.-W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.
6. DAVINCI-2003.06 User Guide, Synopsys, Inc., Mountain View, CA, 2003.
7. V. P. Trivedi, J. G. Fossum, and F. Gámiz, "A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devices," in IEDM Tech. Dig., 2004, pp. 763-766.
8. D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 802-808, Mar. 2003.
9. L. Ge and J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287-294, Feb. 2002.
10. A. Burenkov and J. Lorenz, "On the role of corner effect in FinFETs," in Proc. Eur. Workshop Ultimate Integration Silicon, 2003, pp. 31-34.
11. J.-T. Park and J.-P. Colinge, "Multiple-gate SOI MOSFETs: Device design guidelines," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
12. MEDICI-4.0 Users Manual, Synopsys, Inc., Mountain View, CA, 2002.
13. K. Kim and J. G. Fossum, "Double-gate CMOS: Symmetrical- versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 294-299, Feb. 2001.
14. J. G. Fossum, L. Ge, and M.-H. Chiang, "Speed superiority of scaled double-gate CMOS," IEEE Trans. Electron Devices, vol. 49, no. 5, pp. 808-811, May 2002.
15. "International Technology Roadmap for Semiconductors," Semiconductor Industry Assoc., Austin, TX, 2003.
16. L. Mathew, Private Communication, 2005.