-
1
-
-
29044440093
-
FinFet - A Self-Aligned Double-Gate MOSFET Scalable to 20 nm
-
December
-
D. Hisamoto et al., "FinFet - A Self-Aligned Double-Gate MOSFET Scalable to 20 nm", IEEE Trans. Electron Dev., vol. 47, no. 12, December 2000, pp. 2320-2325
-
(2000)
IEEE Trans. Electron Dev
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
-
2
-
-
41149171855
-
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
-
J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick and R. Chau, "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering", VLSI Tech.Symp., 2006, p. 50-51
-
(2006)
VLSI Tech.Symp
, pp. 50-51
-
-
Kavalieros, J.1
Doyle, B.2
Datta, S.3
Dewey, G.4
Doczy, M.5
Jin, B.6
Lionberger, D.7
Metz, M.8
Rachmady, W.9
Radosavljevic, M.10
Shah, U.11
Zelick, N.12
Chau, R.13
-
3
-
-
0035423513
-
Pi-Gate SOI MOSFET
-
J.-T. Park, J.-P. Colinge and C. H. Diaz, "Pi-Gate SOI MOSFET", IEEE Electron Device Lett., vol. 22, no. 8, 2001, pp. 405
-
(2001)
IEEE Electron Device Lett
, vol.22
, Issue.8
, pp. 405
-
-
Park, J.-T.1
Colinge, J.-P.2
Diaz, C.H.3
-
4
-
-
39549096358
-
A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay Large-Scale Integrated High Performance Digital Circuits and SRAM
-
K. von Arnim et al., "A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay Large-Scale Integrated High Performance Digital Circuits and SRAM", VLSI Tech.Symp., 2007, p. 106-107
-
(2007)
VLSI Tech.Symp
, pp. 106-107
-
-
von Arnim, K.1
-
5
-
-
0036684706
-
FinFET design considerations based on 3-D simulation and analytical modeling
-
G. Pei et al., "FinFET design considerations based on 3-D simulation and analytical modeling", IEEE Trans. Electron Dev., vol. 49, no. 8, 2002, p. 1411-1419
-
(2002)
IEEE Trans. Electron Dev
, vol.49
, Issue.8
, pp. 1411-1419
-
-
Pei, G.1
-
6
-
-
84881738377
-
Challenges in patterning 45nm node multiple-gate devices and SRAM cells
-
M. Ercken, C. Delvaux, C. Baerts, S. Locorotondo, B. Degroote, V. Wiaux, A. Nackaerts, R. Rooyackers, S. Verhaegen and I. Pollentier, "Challenges in patterning 45nm node multiple-gate devices and SRAM cells", Proceedings 41st Interface Symposium
-
Proceedings 41st Interface Symposium
-
-
Ercken, M.1
Delvaux, C.2
Baerts, C.3
Locorotondo, S.4
Degroote, B.5
Wiaux, V.6
Nackaerts, A.7
Rooyackers, R.8
Verhaegen, S.9
Pollentier, I.10
-
7
-
-
38649140309
-
Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
-
M.J.H. Van Dal et al.," Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography", VLSI Tech.Symp., 2007, p. 110-111
-
(2007)
VLSI Tech.Symp
, pp. 110-111
-
-
Van Dal, M.J.H.1
-
8
-
-
46049089837
-
-
R. Rooyackers et al., Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficienty, to be presented at IEDM 2006
-
R. Rooyackers et al., "Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficienty", to be presented at IEDM 2006
-
-
-
-
9
-
-
33745585303
-
Comprehensive approach to MuGFET metrology in Metrology, Inspection, and Process Control for Microlithography XX
-
G. F. Lorusso et al., "Comprehensive approach to MuGFET metrology" in Metrology, Inspection, and Process Control for Microlithography XX, Proc. SPIE 6152, 615219, 2006.
-
(2006)
Proc. SPIE
, vol.6152
, pp. 615219
-
-
Lorusso, G.F.1
-
10
-
-
33745139143
-
Tall Triple-Gate Devices with TiN/HfO2 Gate Stack
-
N. Collaert, M. Demand, I. Ferain, J. Lisoni, R. Singanamalla, P. Zimmerman, Y.S. Yim, T. Schram, G. Mannaert, M. Goodwin, J.C. Hooker, F. Neuilly, M.C. Kim, K. De Meyer, S. De Gendt, W. Boullart, M. Jurczak and S. Biesemans, "Tall Triple-Gate Devices with TiN/HfO2 Gate Stack", VLSI Tech.Symp., 2005, p. 108-109
-
(2005)
VLSI Tech.Symp
, pp. 108-109
-
-
Collaert, N.1
Demand, M.2
Ferain, I.3
Lisoni, J.4
Singanamalla, R.5
Zimmerman, P.6
Yim, Y.S.7
Schram, T.8
Mannaert, G.9
Goodwin, M.10
Hooker, J.C.11
Neuilly, F.12
Kim, M.C.13
De Meyer, K.14
De Gendt, S.15
Boullart, W.16
Jurczak, M.17
Biesemans, S.18
-
11
-
-
85079993265
-
-
IEDM Tech. Dig
-
C.Y.Kang et al., IEDM Tech. Dig., 2006
-
(2006)
-
-
Kang, C.Y.1
-
13
-
-
21044449128
-
Analysis of the Parasitic Source/Drain Resistance in Multiple Gate Field Effect Transistors
-
A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, " Analysis of the Parasitic Source/Drain Resistance in Multiple Gate Field Effect Transistors", IEEE Trans. Electron Dev., vol. 52, no. 6, pp. 1132-1140, 2005
-
(2005)
IEEE Trans. Electron Dev
, vol.52
, Issue.6
, pp. 1132-1140
-
-
Dixit, A.1
Kottantharayil, A.2
Collaert, N.3
Goodwin, M.4
Jurczak, M.5
De Meyer, K.6
-
14
-
-
37149004390
-
2/TiN FinFET devices: A View on GIDL (Gate-Induced Drain Leakage) and Schottky Barriers S/D Leakages
-
2/TiN FinFET devices: a View on GIDL (Gate-Induced Drain Leakage) and Schottky Barriers S/D Leakages", IEDM Tech. Dig., pp.743-746, 2005
-
(2005)
IEDM Tech. Dig
, pp. 743-746
-
-
Hoffmann, T.1
-
16
-
-
39549118253
-
Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions
-
D. Lenoble et al., "Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions", VLSI Tech.Symp., 2006, p. 168-169
-
(2006)
VLSI Tech.Symp
, pp. 168-169
-
-
Lenoble, D.1
-
17
-
-
3943054085
-
Improvement of FinFET Electrical Characteristics by Hydrogen Annealing
-
Weize Xiong, Gabriel Gebara, Joyti Zaman, Michael Gostkowski, Billy Nguyen, Greg Smith, David Lewis, C. Rinn Cleavelin, Rick Wise, Shaofeng Yu, Michael Pas, Tsu-Jae King, and J. P. Colinge, "Improvement of FinFET Electrical Characteristics by Hydrogen Annealing", IEEE Electron Dev. Lett., vol. 25, no. 8, pp. 541-543, 2004
-
(2004)
IEEE Electron Dev. Lett
, vol.25
, Issue.8
, pp. 541-543
-
-
Xiong, W.1
Gebara, G.2
Zaman, J.3
Gostkowski, M.4
Nguyen, B.5
Smith, G.6
Lewis, D.7
Rinn Cleavelin, C.8
Wise, R.9
Yu, S.10
Pas, M.11
King, T.-J.12
Colinge, J.P.13
-
18
-
-
33847712546
-
-
K. Shin, C. O. Chui and T.-J. King, Dual Stress Capping Layer Enhancement Study for Hybrid Orientation FinFET CMOS Technology, IEDM Tech. Dig., pp., 2005
-
K. Shin, C. O. Chui and T.-J. King," Dual Stress Capping Layer Enhancement Study for Hybrid Orientation FinFET CMOS Technology", IEDM Tech. Dig., pp., 2005
-
-
-
-
19
-
-
27744582205
-
Performance improvement of Tall Triple Gate devices with strained SiN layers
-
N. Collaert, A. De Keersgieter, K.G. Anil, R. Rooyackers, G. Eneman, M. Goodwin, B. Eyckens, E. Sleeckx, J.-F. de Marneffe, K. De Meyer, P. Absil, M. Jurczak and S. Biesemans, "Performance improvement of Tall Triple Gate devices with strained SiN layers", IEEE Electron Dev. Lett., vol. 26, no. 11, pp. 820-822, 2005
-
(2005)
IEEE Electron Dev. Lett
, vol.26
, Issue.11
, pp. 820-822
-
-
Collaert, N.1
De Keersgieter, A.2
Anil, K.G.3
Rooyackers, R.4
Eneman, G.5
Goodwin, M.6
Eyckens, B.7
Sleeckx, E.8
de Marneffe, J.-F.9
De Meyer, K.10
Absil, P.11
Jurczak, M.12
Biesemans, S.13
-
20
-
-
21644472774
-
2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
-
2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography", IEDM Techn. Dig., 2004, p. 269-272
-
(2004)
IEDM Techn. Dig
, pp. 269-272
-
-
Nackaerts, A.1
-
21
-
-
33745171087
-
2 6T-SRAM Cell and advanced CMOS Logic circuits
-
2 6T-SRAM Cell and advanced CMOS Logic circuits", VLSI Tech.Symp., 2005, p. 106-107
-
(2005)
VLSI Tech.Symp
, pp. 106-107
-
-
Witters, L.1
-
22
-
-
33846573973
-
Device and circuit-level analog performance trade-offs: A comparative study of planar bulk FETs versus FinFETs
-
V. Subramanian et al., "Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs", IEDM Tech. Dig., 2005, p. 898-901
-
(2005)
IEDM Tech. Dig
, pp. 898-901
-
-
Subramanian, V.1
-
23
-
-
34250680414
-
Stochastic Matching Properties of FinFETs",
-
C. Gustin et al., "Stochastic Matching Properties of FinFETs",", IEEE Electron Dev. Lett., vol. 27, no. 10, pp. 846-848, 2006
-
(2006)
IEEE Electron Dev. Lett
, vol.27
, Issue.10
, pp. 846-848
-
-
Gustin, C.1
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