Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Rooyackers, R ^a   Augendre, E ^a   Degroote, B ^a   Collaert, N ^a   Nackaerts, A ^a   Dixit, A ^a,b   Vandeweyer, T ^a   Pawlak, B ^a,c   Ercken, M ^a   Kunnen, E ^a   Dilliway, G ^a   Leys, F ^a   Loo, R ^a   Jurczak, M ^a   Biesemans, S ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; FINS (HEAT EXCHANGE); PHOTOLITHOGRAPHY; SILICON;

CD VARIATIONS; CD-CONTROL; DRIVE CURRENTS; FIN DENSITY; FIN PITCH; INTEGRATION SCHEMES; LINE-WIDTH ROUGHNESS; MULTIPLE-GATE; OPTICAL LITHOGRAPHY; PATTERN FIDELITY; PATTERNING METHODS;

FIELD EFFECT TRANSISTORS;

EID: 46049089837     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346954     Document Type: Conference Paper

References (8)

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3. Y.-K. Choi, Tsu-Jae King and Chenning Hu, " A Spacer Patterning Technology for Nanoscale CMOS", IEEE Trans. El. Dev., 2002-49, pp. 436-441
4. H. Park et al., "High Performance CMOS Devices on SOI for 90 nm Technology Enhanced by RSD and Thermal Cycle/Spacer Engineering", IEDM Tech. Digest, 2003, pp. 27.4.1-27.4.4.
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6. H. Shang et al., "Investigation of FinFET devices for 32nm technologies and beyond", VLSI symp., 2006, pp. 66-67
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8. A. Dixit et al., these proceedings, IEDM 2006