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Volumn 6152 I, Issue , 2006, Pages

Comprehensive approach to MuGFET metrology

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); METRIC SYSTEM; SCATTERING; SURFACE ROUGHNESS;

EID: 33745585303     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.656076     Document Type: Conference Paper
Times cited : (6)

References (3)
  • 1
    • 4344643528 scopus 로고    scopus 로고
    • Sub-50-nm isolated line and trench width artifacts for CD metrology
    • Metrology, Inspection, and Process Control for Microlithography XVIII. Edited by Silver, Richard M.
    • M. Tortonese, G.F. Lorusso, R.M. Blanquies, J. Prochazka; L. Grella, "Sub-50-nm isolated line and trench width artifacts for CD metrology" Metrology, Inspection, and Process Control for Microlithography XVIII. Edited by Silver, Richard M. Proceedings of the SPIE, vol 5375, pp. 647-656, 2004.
    • (2004) Proceedings of the SPIE , vol.5375 , pp. 647-656
    • Tortonese, M.1    Lorusso, G.F.2    Blanquies, R.M.3    Prochazka, J.4    Grella, L.5
  • 2
    • 0036927513 scopus 로고    scopus 로고
    • Line edge roughness: Characterization, modeling and impact on device behavior
    • IEDM
    • J. Croon et al., Line Edge Roughness: Characterization, Modeling and Impact on Device Behavior, IEDM, Electron Devices Meeting, p307-310, 2002
    • (2002) Electron Devices Meeting , pp. 307-310
    • Croon, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.