Stochastic matching properties of FinFETs

IEEE Electron Device Letters

Volumn 27, Issue 10, 2006, Pages 846-848

  Gustin, C ^a   Mercha, A ^a   Loo, J ^a   Subramanian, V ^b   Parvais, B ^a   Dehan, M ^a   Decoutere, S ^a  

^a IMEC   (Belgium)

^b Katholieke Universiteit Leuven   (Belgium)

Author keywords

Device mismatch; Double gate; FinFET; Intrinsic parameter fluctuation; Series resistance

Indexed keywords

DEVICE MISMATCH; DOUBLE GATE; FINFET; INTRINSIC PARAMETER FLUCTUATION; SERIES RESISTANCE;

FINS (HEAT EXCHANGE);

FIELD EFFECT TRANSISTORS;

EID: 34250680414     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.882524     Document Type: Article

References (10)

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
2. V. Subramanian, B. Parvais, J. Borremans, A.Mercha, and D. Linten et al., "Device and circuit-level analog performance trade-offs: A comparative study of planar bulk FETs versus FinFETs," in IEDM Tech. Dig., 2005, pp. 919-922.
3. P. G. Drennan and C. C. McAndrew, "Understanding MOSFET mismatch for analog design," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450-456, Mar. 2003.
4. J. Bastos, M. Steyaert, A. Pergoot, and W. Sansen, "Mismatch characterization of submicron MOS transistors," Analog Integr. Circuits Signal Process., vol. 12, no. 2, pp. 95-106, Feb. 1997.
5. J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, and H. E. Maes, "An easy-to-use mismatch model for the MOS transistor," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1056-1064, Aug. 2002.
6. T. Serrano-Gotarredona and B. Linares-Barranco, "Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation," Analog Integr. Circuits Signal Process, vol. 21, no. 3, pp. 271-296, Dec. 1999.
7. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
8. G. S. Lujan, S. Kubicek, S. De Gendt, M. Heyns, W. Magnus, and K. De Meyer, "Mobility degradation in high-κ transistors: The role of the charge scattering," in Proc. ESSDERC, 2003, pp. 399-402.
9. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
10. J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd ed. Norwell, MA: Kluwer, 2004.