Dual stress capping layer enhancement study for hybrid orientation FinFET CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 988-991

  Shin, Kyoungsub ^a   Chui, Chi On ^b   King, Tsu Jae ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FINFET CMOS TECHNOLOGY; HYBRID ORIENTATION; MOBILITY ENHANCEMENT; STRESSED CAPPING LAYERS;

ASPECT RATIO; ELECTRON MOBILITY; FIELD EFFECT TRANSISTORS; HOLE MOBILITY; PIEZOELECTRIC DEVICES; STRESS ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 33847712546     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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