Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

IEEE Electron Device Letters

Volumn 26, Issue 3, 2005, Pages 197-199

  Choi, Rino ^a   Rhee, Se Jong ^b   Lee, Jack C ^b   Lee, Byoung Hun ^c   Bersuker, Gennadi ^a  

^a SEMATECH   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c IBM   (United States)

Author keywords

AC stress; Charge trap; High dielectric; Relaxation

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENT MEASUREMENT; HAFNIUM COMPOUNDS; MEASUREMENT ERRORS; PERMITTIVITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; STRESSES; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

AC STRESS; CHARGE TRAP; GATE STACK; VOLTAGE STRESS;

MOSFET DEVICES;

EID: 15544374381     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.842639     Document Type: Article

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