Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 26-29

  Keshavarzi, Ali ^a   Schrom, Gerhard ^a   Tang, Stephen ^a   Ma, Sean ^c   Bowman, Keith ^b   Tyagi, Sunit ^b   Zhang, Kevin ^b   Linton, Tom ^b   Hakim, Nagib ^b   Duvall, Steven ^b   Brews, John ^c   De, Vivek ^a  

^a INTEL RESEARCH   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF ARIZONA   (United States)

Author keywords

Body Bias; CMOS; Integrated Circuits; Mismatch; Process Variation; Random Dopant Variation; Threshold Voltage; Threshold Voltage Variation; Transistor Mismatch; Transistor threshold voltage mismatch; Transistors; Variation; Vt; Vt Mismatch; Vt Variation

Indexed keywords

COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; MEASUREMENT THEORY; TRANSISTORS;

BODY BIAS; MISMATCH; PROCESS VARIATION; TRANSISTOR MISMATCH; VARIATION; VT; VT MISMATCH; VT VARIATION;

MOSFET DEVICES;

EID: 28444497846     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195480     Document Type: Conference Paper

References (4)

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4. D. Burnett, et. al., 1994 VLSI Technology Symposium, pp. 15-16.