Timing error correction techniques for voltage- scalable on-chip memories

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 3563-3566

  Karl, Eric ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT TECHNIQUES; CONVENTIONAL DESIGN; CORRECTION TECHNIQUES; CRITICAL PATHS; CRITICAL VOLTAGES; ENERGY BUDGETS; ERROR RECOVERY; MEMORY ACCESS DELAY; ON CHIP MEMORY; POWER SAVINGS; PROCESS VARIATION; SENSING SCHEMES; SIMULATION RESULT; SUPPLY VOLTAGE VARIATION; SUPPLY VOLTAGES; TEMPERATURE FLUCTUATION; TIMING ERRORS; VOLTAGE-SCALING;

TIME MEASUREMENT; TIMING CIRCUITS;

ERROR CORRECTION;

EID: 67649120062     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465399     Document Type: Conference Paper

References (7)

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