A self-tuning DVS processor using delay-error detection and correction

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 258-261

  Das, Shidhartha ^a   Pant, Sanjay ^a   Roberts, David ^a   Lee, Seokwoo ^a   Blaauw, David ^a   Austin, Todd ^a   Mudge, Trevor ^a   Flautner, Krisztian ^b  

^a Department of Ecology and Evolutionary Biology   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY-ERROR DETECTION; DVS PROCESSOR; ERROR RATE; SILICON MEASUREMENTS;

ELECTRIC POTENTIAL; ERROR CORRECTION; ERROR DETECTION; NATURAL FREQUENCIES; TUNING; VOLTAGE CONTROL;

VOLTAGE REGULATORS;

EID: 33645684412     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469380     Document Type: Conference Paper

References (7)

1. D. Ernst, et. al., pp.7-18, MICRO 36.
2. K. Suzuki, et. al., pp. 587-590, CICC 97
3. S. Sakiyama, et. al., pp. 99-100, Symposium on VLSI circuits, 1997
4. T. Burd, et. al., pp.294-295, ISSCC, 2000.
5. S. Akui, et. al., pp.64-65, ISSCC 2004.
6. Nowka, et. al., pp.340-341, ISSCC 2002
7. www.mosis.org