메뉴 건너뛰기




Volumn 1, Issue , 2006, Pages

Test set enrichment using a probabilistic fault model and the theory of output deviations

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; GATES (TRANSISTOR); INTEGRATED CIRCUITS; PROBABILISTIC LOGICS;

EID: 34047119227     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (24)
  • 2
    • 33947698137 scopus 로고    scopus 로고
    • New defect behavior at 130nm and beyond
    • R. Aitken, 'New defect behavior at 130nm and beyond," in Proc. European Test Symposium, 2004, pp. 279-284.
    • (2004) Proc. European Test Symposium , pp. 279-284
    • Aitken, R.1
  • 3
    • 0030215849 scopus 로고    scopus 로고
    • GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuits
    • Aug
    • F. Corno, P. Prinetto, M. Rebaudengo, and M. S. Reorda, "GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits," IEEE Trans. CAD, p. 943, Aug. 1996.
    • (1996) IEEE Trans. CAD , pp. 943
    • Corno, F.1    Prinetto, P.2    Rebaudengo, M.3    Reorda, M.S.4
  • 5
    • 84893736371 scopus 로고    scopus 로고
    • Delay fault testing of core-based systems-on-a-chip
    • Q. Xu and N. Nicolici, "Delay fault testing of core-based systems-on-a-chip,"in Proc. DATE Conf., 2003, pp. 744-749.
    • (2003) Proc. DATE Conf , pp. 744-749
    • Xu, Q.1    Nicolici, N.2
  • 6
    • 0033316853 scopus 로고    scopus 로고
    • Pattern sensitivity: A property to guide test generation for combinational circuits
    • I. Pomeranz and S. M. Reddy, 'Pattern sensitivity: A property to guide test generation for combinational circuits," in Proc. 8th Asian Test Symp., 1999, pp. 75-80.
    • (1999) Proc. 8th Asian Test Symp , pp. 75-80
    • Pomeranz, I.1    Reddy, S.M.2
  • 7
    • 33847158716 scopus 로고    scopus 로고
    • An optimal test pattern selection method to improve the defect coverage
    • Y. Tian, M. Mercer, W. Shi, and M. Grimaila, "An optimal test pattern selection method to improve the defect coverage," in Proc. Int. Test Conf., 2005.
    • (2005) Proc. Int. Test Conf
    • Tian, Y.1    Mercer, M.2    Shi, W.3    Grimaila, M.4
  • 8
    • 0003133883 scopus 로고
    • Probabilistic logics and the synthesis of reliable organisms from unreliable components
    • Princeton University Press, Princeton, NJ
    • J. von Neumann, "Probabilistic logics and the synthesis of reliable organisms from unreliable components," in C. E. Shannon and J. McCarthy, ed., Automata Studies. Princeton University Press, Princeton, NJ, 1956, pp. 43-98.
    • (1956) C. E. Shannon and J. McCarthy, ed., Automata Studies , pp. 43-98
    • von Neumann, J.1
  • 11
  • 12
    • 0012223405 scopus 로고    scopus 로고
    • A system architecture solution for unreliable nanoelectronic devices
    • December
    • J. Han and P. Jonker, "A system architecture solution for unreliable nanoelectronic devices," IEEE Trans. on Nanotechnology, vol. 1, pp. 201-208, December 2002.
    • (2002) IEEE Trans. on Nanotechnology , vol.1 , pp. 201-208
    • Han, J.1    Jonker, P.2
  • 13
    • 0030213622 scopus 로고    scopus 로고
    • Fully parallel stochastic computation architecture
    • August
    • C. L. Janer et al., "Fully parallel stochastic computation architecture," IEEE Trans. on Signal Processing, vol. 44, pp. 2110-2117, August 1996.
    • (1996) IEEE Trans. on Signal Processing , vol.44 , pp. 2110-2117
    • Janer, C.L.1
  • 15
    • 0036931372 scopus 로고    scopus 로고
    • Modeling the effect of technology trends on the soft error rate of combinational logic
    • P. Shivakumar et al., "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proc. Int. Conf. Dependable Systems and Networks, 2002, pp. 389-398.
    • (2002) Proc. Int. Conf. Dependable Systems and Networks , pp. 389-398
    • Shivakumar, P.1
  • 16
    • 0142184763 scopus 로고    scopus 로고
    • Cost-effective approach for reducing soft error failure rate in logic circuits
    • K. Mohanram and N. A. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," in Proc. Int. Test Conf., 2003.
    • (2003) Proc. Int. Test Conf
    • Mohanram, K.1    Touba, N.A.2
  • 17
    • 34047139061 scopus 로고    scopus 로고
    • White Paper: New trends and solutions to combat the soft error threat to ICs in 2004, iRoC Technologies, www.iroc.com, 2004.
    • White Paper: New trends and solutions to combat the soft error threat to ICs in 2004, iRoC Technologies, www.iroc.com, 2004.
  • 18
    • 15044363155 scopus 로고    scopus 로고
    • Robust system design with built-in soft-error resilience
    • Feb
    • S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, "Robust system design with built-in soft-error resilience," IEEE Computer, pp. 43-52, Feb. 2005.
    • (2005) IEEE Computer , pp. 43-52
    • Mitra, S.1    Seifert, N.2    Zhang, M.3    Shi, Q.4    Kim, K.S.5
  • 20
    • 0024108354 scopus 로고
    • A CMOS fault extractor for inductive fault analysis
    • Nov
    • F. J. Ferguson and J. P. Shen, "A CMOS fault extractor for inductive fault analysis," IEEE Trans. CAD, vol. 7, pp. 1181-1194, Nov. 1988.
    • (1988) IEEE Trans. CAD , vol.7 , pp. 1181-1194
    • Ferguson, F.J.1    Shen, J.P.2
  • 21
    • 0016521521 scopus 로고
    • Probabilistic treatment of general combinational networks
    • June
    • K. P. Parker and E. J. McCluskey, "Probabilistic treatment of general combinational networks," IEEE Trans. Computers, pp. 668-670, June 1975.
    • (1975) IEEE Trans. Computers , pp. 668-670
    • Parker, K.P.1    McCluskey, E.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.