Logic circuit testing for transient faults

Proceedings of the 10th IEEE European Test Symposium, ETS 2005

Volumn 2005, Issue , 2005, Pages 102-107

  Krishnaswamy, Smita ^a   Markov, Igor L ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MATRIX-BASED GATE-FAULT MODEL; PROBABILISTIC TRANSFER MATRIX MODEL; TRANSIENT ERRORS;

ELECTRIC FAULT CURRENTS; ERROR ANALYSIS; MATHEMATICAL MODELS; MATRIX ALGEBRA; NEUTRONS; PROBABILITY DISTRIBUTIONS;

LOGIC CIRCUITS;

EID: 33744501280     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2005.27     Document Type: Conference Paper

References (10)

1. L. Geppert "Chip Making's Wet New World," IEEE Spectrum May, 2004.
2. H. K. Lee and D. S. Ha, "On the Generation of Test Patterns for Combinational Circuits," Technical Report No. 12-93, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University.
3. V. L. Levin,"Probability Analysis of Combination Systems and their Reliability,"Engin. Cybernetics, no 6. Nov-Dec. 1964, pp. 78-84.
4. S. Krishnaswamy, G. F. Viamontes, I. L. Markov and J. P. Hayes, "Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices", Proc. DATE, March 2005, pp. 282-287.
5. C. Metra, S. D. Francescantonio, G. Maralle. "On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits" DFT, 2002, pp. 205-217.
6. K. Mohanram and N. A. Touba, "Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits," Proc. ITC, 2003, pp. 893-901.
7. K.M. Patel, J.P. Hayes, and I.L. Markov, "Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models," Proc. IWLS, May 2003, pp. 59-64.
8. S. Reddy, I. Pomeranz, S. Kajihara "Compact Test Sets for High Defect Coverage" IEEE Trans. on CAD of ICs and Systems vol.16 no. 8, 1997, pp. 923-930.
9. P. Shivakumar, et al., "Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic" Proc. DSN, 2002, pp. 389-398.
10. H.-J. Wunderlich and G. Kiefer "Bit-Flipping BIST," Proc. ICCAD, 1996, 337-343.