An evaluation of pseudo random testing for detecting real defects

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 404-409

  Tseng, C W ^a   Mitra, S ^a   Davidson, S ^a   McCluskey, E J ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; EVALUATION; INTEGRATED CIRCUIT TESTING; SIMULATION; VLSI CIRCUITS;

N-DETECT COVERAGE; PSEUDO RANDOM TESTING; PSEUDO-RANDOM PATTERNS;

BUILT-IN SELF TEST;

EID: 0034995210     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Quantifying non-target defect detection by target fault test sets
2. REDO-random exicitation and deterministic observation - First commercial experiment
3. ITC Lecture Series
4. ELF35 experiment - Chip and experiment design
5. An experimental chip to evaluate test techniques: Experimental results
6. Built-in self test structures
7. Probability model for pseudo random test sequence
8. Stuck-at test vs. real defects
9. Stuck-at tuple-detection: A fault model based on stuck-at faults for improved defect coverage
10. Alternating a pseudo-random bit sequence for scan-based BIST
11. A method for generating weighted random test patterns