-
1
-
-
12344302272
-
On-line BIST and BIST-based diagnosis of FPGA logic blocks
-
Dec
-
M. Abramovici, C. Stroud, and J. Emmert, "On-line BIST and BIST-based diagnosis of FPGA logic blocks," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 12, pp. 1284-1294, Dec. 2004.
-
(2004)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.12
, Issue.12
, pp. 1284-1294
-
-
Abramovici, M.1
Stroud, C.2
Emmert, J.3
-
2
-
-
0035242889
-
BIST-based test and diagnosis of FPGA logic blocks
-
Feb
-
M. Abramovici and C. Stroud, "BIST-based test and diagnosis of FPGA logic blocks," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 159-172, Feb. 2001.
-
(2001)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.9
, Issue.1
, pp. 159-172
-
-
Abramovici, M.1
Stroud, C.2
-
3
-
-
84960389355
-
Improving on-line BIST-based diagnosis for roving STARs
-
M. Abramovici, C. Stroud, B. Skaggs, and J. Emmert, "Improving on-line BIST-based diagnosis for roving STARs," in Proc. 6th IEEE Int. On-Line Testing Workshop, 2000, pp. 31-39.
-
(2000)
Proc. 6th IEEE Int. On-Line Testing Workshop
, pp. 31-39
-
-
Abramovici, M.1
Stroud, C.2
Skaggs, B.3
Emmert, J.4
-
4
-
-
0033335486
-
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications
-
Sep
-
M. Abramovici, C. Stroud, S. Wijesuriya, and V. Verma, "Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications," in Proc. IEEE Int. Test Conf., Sep. 1999, pp. 973-982.
-
(1999)
Proc. IEEE Int. Test Conf
, pp. 973-982
-
-
Abramovici, M.1
Stroud, C.2
Wijesuriya, S.3
Verma, V.4
-
5
-
-
0036907236
-
Molecular electronics: Devices, systems and tools for gigagate, gigabit chips
-
M. Butts, A. DeHon, and S. C. Goldstein, "Molecular electronics: Devices, systems and tools for gigagate, gigabit chips," in Proc. Int. Conf. Comput. -Aided Des., 2002, pp. 433-440.
-
(2002)
Proc. Int. Conf. Comput. -Aided Des
, pp. 433-440
-
-
Butts, M.1
DeHon, A.2
Goldstein, S.C.3
-
6
-
-
0036826706
-
A search-based bump-and-refit approach to incremental routing for ECO applications in EPGAs
-
Oct
-
S. Dutt, V. Verma, and H. Arslan, "A search-based bump-and-refit approach to incremental routing for ECO applications in EPGAs," ACM Trans. Des. Autom. Electron. Syst., vol. 7, no. 4, pp. 664-693, Oct. 2002.
-
(2002)
ACM Trans. Des. Autom. Electron. Syst
, vol.7
, Issue.4
, pp. 664-693
-
-
Dutt, S.1
Verma, V.2
Arslan, H.3
-
7
-
-
0033352290
-
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays
-
S. Dutt, V. Shanmugavel, and S. Trimberger, "Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays," in Proc. IEEE Int. Conf. Comput.-Aided Des., 1999, pp. 173-176.
-
(1999)
Proc. IEEE Int. Conf. Comput.-Aided Des
, pp. 173-176
-
-
Dutt, S.1
Shanmugavel, V.2
Trimberger, S.3
-
8
-
-
0034845496
-
NanoFabrics: Spatial computing using molecular electronics
-
S. C. Goldstein and M. Budiu, "NanoFabrics: Spatial computing using molecular electronics," in Proc. Int. Symp. Comput. Archit, 2001, pp. 178-189.
-
(2001)
Proc. Int. Symp. Comput. Archit
, pp. 178-189
-
-
Goldstein, S.C.1
Budiu, M.2
-
9
-
-
0031649068
-
Methodologies for tolerating cell and interconnect faults in FPGAs
-
Jan
-
F. Hanchek and S. Dutt, "Methodologies for tolerating cell and interconnect faults in FPGAs," IEEE Trans. Comput.-Special Issue Dependable Comput, vol. 47, no. 1, pp. 15-33, Jan. 1998.
-
(1998)
IEEE Trans. Comput.-Special Issue Dependable Comput
, vol.47
, Issue.1
, pp. 15-33
-
-
Hanchek, F.1
Dutt, S.2
-
10
-
-
0032099764
-
Testing configurable LUT-based FPGAs
-
Jun
-
W. K. Huang, F. J. Meyer, X. Chen, and F. Lombardi, "Testing configurable LUT-based FPGAs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 2, pp. 276-283, Jun. 1998.
-
(1998)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.6
, Issue.2
, pp. 276-283
-
-
Huang, W.K.1
Meyer, F.J.2
Chen, X.3
Lombardi, F.4
-
11
-
-
0031655580
-
Universal fault diagnosis for lookup table FPGAs
-
Jan.Mar
-
T. Inoue and H. Fujiwara, "Universal fault diagnosis for lookup table FPGAs," IEEE Des. Test Comput., vol. 15, no. 1, pp. 39-44, Jan.Mar. 1998.
-
(1998)
IEEE Des. Test Comput
, vol.15
, Issue.1
, pp. 39-44
-
-
Inoue, T.1
Fujiwara, H.2
-
12
-
-
0032628982
-
An overview of manufacturing yield and reliability modeling for semiconductor products
-
Aug
-
W. Kuo and T. Kim, "An overview of manufacturing yield and reliability modeling for semiconductor products," Proc. IEEE, vol. 87, no. 8, pp. 1329-1344, Aug. 1999.
-
(1999)
Proc. IEEE
, vol.87
, Issue.8
, pp. 1329-1344
-
-
Kuo, W.1
Kim, T.2
-
13
-
-
0032096706
-
Low overhead faulttolerant FPGA systems
-
Jun
-
J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Low overhead faulttolerant FPGA systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 2, pp. 212-221, Jun. 1998.
-
(1998)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.6
, Issue.2
, pp. 212-221
-
-
Lach, J.1
Mangione-Smith, W.H.2
Potkonjak, M.3
-
14
-
-
0032597687
-
Efficient network-flow based techniques for dynamic fault reconfiguration in FPGAs
-
N. R. Mahapatra and S. Dutt, "Efficient network-flow based techniques for dynamic fault reconfiguration in FPGAs," in Proc. 29th Int. Symp. Fault-Tolerant Comput., 1999, pp. 122-129.
-
(1999)
Proc. 29th Int. Symp. Fault-Tolerant Comput
, pp. 122-129
-
-
Mahapatra, N.R.1
Dutt, S.2
-
15
-
-
84938017623
-
On the connection assignment problem of diagnosable systems
-
Dec
-
F. P. Preparata, G. Metze, and R. T. Chen, "On the connection assignment problem of diagnosable systems," IEEE Trans. Electron. Comput., vol. EC-16, no. 6, pp. 848-854, Dec. 1967.
-
(1967)
IEEE Trans. Electron. Comput
, vol.EC-16
, Issue.6
, pp. 848-854
-
-
Preparata, F.P.1
Metze, G.2
Chen, R.T.3
-
16
-
-
0032293995
-
On-line fault detection for bus-based field programmable gate arrays
-
Dec
-
N. R. Shnidman, W. H. Mangione-Smith, and M. Potkonjak, "On-line fault detection for bus-based field programmable gate arrays," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 656-666, Dec. 1998"
-
(1998)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.6
, Issue.4
, pp. 656-666
-
-
Shnidman, N.R.1
Mangione-Smith, W.H.2
Potkonjak, M.3
-
17
-
-
0021782318
-
The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions
-
Jan
-
C. H. Stapper, "The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions," IBM J. Res. Develop., vol. 29, no. 1, pp. 87-97, Jan. 1985.
-
(1985)
IBM J. Res. Develop
, vol.29
, Issue.1
, pp. 87-97
-
-
Stapper, C.H.1
-
18
-
-
85013621311
-
On-line BIST and diagnosis of FPGA interconnect using roving STARs
-
C. Stroud et al., "On-line BIST and diagnosis of FPGA interconnect using roving STARs," in Proc. IEEE Int. On-Line Test Workshop, 2001, pp. 27-33.
-
(2001)
Proc. IEEE Int. On-Line Test Workshop
, pp. 27-33
-
-
Stroud, C.1
-
19
-
-
34047175434
-
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults
-
Mar
-
V. Suthar and S. Dutt, "Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults," in Proc. DATE, Mar. 2006, pp. 1165-1170.
-
(2006)
Proc. DATE
, pp. 1165-1170
-
-
Suthar, V.1
Dutt, S.2
-
20
-
-
4444343543
-
Efficient on-line testing of FPGAs with provable diagnosabilities
-
nominated for a best paper award
-
V. Verma, S. Dutt, and V. Suthar, "Efficient on-line testing of FPGAs with provable diagnosabilities," in Proc. DAC, 2004, pp. 498-503. nominated for a best paper award.
-
(2004)
Proc. DAC
, pp. 498-503
-
-
Verma, V.1
Dutt, S.2
Suthar, V.3
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