A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs

ACM Transactions on Design Automation of Electronic Systems

Volumn 7, Issue 4, 2002, Pages 664-693

  Dutt, Shantanu ^a   Verma, Vinay ^a   Arslan, Hasan ^a  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

Bump and refit (B R) paradigm; Bumping cost; Detailed routing; Dynamic programming; ECO (engineering change order); Field programmable gate arrays; Global routing; Incremental routing; Switchbox

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; DYNAMIC PROGRAMMING; INTEGRATED CIRCUITS; ROUTERS;

INCREMETAL ROUTING METHOD;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036826706     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/605440.605449     Document Type: Article

References (9)

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