Methodologies for tolerating cell and interconnect faults in FPGAs

IEEE Transactions on Computers

Volumn 47, Issue 1, 1998, Pages 15-33

  Hanchek, Fran ^a,b   Dutt, Shantanu ^a,c  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c 1120 Science and Engineering Offices   (United States)

Author keywords

Cell faults; Fault tolerance; Field Programmable Gate Array (FPGA); Reconfiguration; Wiring faults; Yield improvement

Indexed keywords

FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

CELL FAULTS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); WIRING FAULTS;

CELLULAR ARRAYS;

EID: 0031649068     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.656073     Document Type: Article

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