Statistical clock skew analysis considering intradie-process variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 8, 2004, Pages 1231-1242

  Agarwal, Aseem ^a   Zolotov, Vladimir ^b   Blaauw, David T ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b MOTOROLA INC   (United States)

Author keywords

Clock skew; Probability; Process variation; Statistical analysis

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; MONTE CARLO METHODS; TIMING CIRCUITS;

CLOCK SKEW ANALYSIS; CLOCK TREE CIRCUITS; HIGH PERFORMANCE MICROPROCESSORS; INTRADIE PROCESS VARIATIONS;

INTEGRATED CIRCUITS;

EID: 3843141621     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.831573     Document Type: Article

References (32)

1. J. Cong, A. B. Kahng, C. K. Koh, and C.-W. A. Tsao, "Bounded-skew clock and Steiner routing," in ACM Trans. Design Automation Electron. Syst., vol. 3, 1998, pp. 341-388.
2. T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. Circuits Syst., vol. 39, pp. 799-814, Nov. 1992.
3. B. Lu, J. Hu, G. Ellis, and H. Su, "Process variation aware clock tree routing," in Proc. IEEE/ACM Int. Symp. Phys. Design, 2003, pp. 174-181.
4. I. M. Liu, T. L. Chou, A. Aziz, and D. F. Wong, "Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion," in Proc. IEEE/ACM Int. Symp. Phys. Design, Apr. 2000, pp. 33-38.
5. S. Pullela, N. Menezes, and L. T. Pillage, "Reliable nonzero skew clock trees using wire width optimization," in Proc. Design Automation Conf., 1993, pp. 165-170.
6. R. S. Tsay, "An exact zero-skew clock routing algorithm," IEEE Trans. Computer-Aided Design, vol. 12, pp. 242-249, Feb. 1993.
7. S. Lin and C. K. Wong, "Process-variation-tolerant clock skew minimization," in Proc. IEEE Int. Conf. Computer-Aided Design, 1994, pp. 284-288.
8. M. Edahiro, "A clustering-based optimization algorithm in zero-skew routings," in Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 612-616.
9. G. Bai, S. Bobba, and I. N. Hajj, "Static timing analysis including power supply noise effect on propagation delay in VLSI circuits," in Proc. IEEE/ACM Design Automation Conf., 2001, pp. 295-300.
10. M. Zhao, K. Gala, V. Zolotov, Y. Fu, R. Panda, R. Ramkumar, and B. Agarwal, "Worst case clock skew under power supply variations," Proc. TAU, pp. 22-28, Dec. 2002.
11. S. Nassif, "Delay variability: Sources, impacts and trends," in Proc. ISSCC, 2000.
12. A. Kahng and Y. Pati, "Subwavelength optical lithography: Challenges and impacts on physical design," in Proc. Int. Symp. Phys. Design, 1999, pp. 112-119.
13. D. Boning and J. Chung, "Statistical metrology-tools for understanding spatial variation," in Proc. SPIE Symp. Microelectron. Manufact., Oct. 1996, pp. 16-26.
14. M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits," in Proc. Int. Conf. Computer-Aided Design, 2000, pp. 62-67.
15. V. Mehrotra, S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif, "A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance," in Proc. Design Automation Conf., 2000, pp. 172-175.
16. Y. Liu, S. Nassif, L. T. Pileggi, and A. J. Strojwas, "Impact of interconnect variations on the clock skew of a gigahertz microprocessor," in Proc. Design Automation Conf., 2000, pp. 168-171.
17. E. Malavasi, S. Zanella, M. Cao, J. Uschersohn, M. Misheloff, and C. Guardiani, "Impact analysis of process variability on clock skew," in Proc. Int. Symp. Quality Electron. Design, 2002, pp. 129-132.
18. X. Jiang and S. Horiguchi, "A probabilistic approach to modeling skews and the largest delays of general clock distribution networks," in Proc. ACM/IEEE Int. Workshop Timing Issues Specification Synthesis Dig. Syst. (TAU) 2000, Dec. 2000, pp. 21-26.
19. X. Jiang and S. Horiguchi, "Statistical skew modeling for general clock distribution networks in presence of process variations," IEEE Trans. VLSI Systems, vol. 9, pp. 704-717, Oct. 2001.
20. D. Harris and S. Naffziger, "Statistical clock skew modeling with data delay variations," IEEE Trans. VLSI Systems, vol. 9, pp. 888-898, Dec. 2001.
21. J. J. Liou, K. T. Cheng, S. Kundu, and A. Krstic, "Fast statistical timing analysis by probabilistic even propagation," in Proc. Design Automation Conf., 2001, pp. 661-666.
22. A. Gattiker, S. Nassif, R. Dinakar, and C. Long, "Timing yield estimation from static timing analysis," in Proc. ISQED, 2001, pp. 437-442.
23. S. Devadas, H. F. Jyu, K. Keutzer, and S. Malik, "Statistical timing analysis of combinational circuits," in Proc. ICCD, 1992, pp. 38-43.
24. M. Orshansky and K. Keutzer, "A general probabilistic framework for worst-case timing analysis," in Proc. Design Automation Conf., 2002, pp. 556-561.
25. M. Berkelaar, "Statistical delay calculation, a linear time method," in Proc. TAU, 1997, pp. 15-24.
26. A. Agarwal, D. Blaauw, S. Sundareswaran, V. Zolotov, M. Zhou, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," in Proc. Asia South Pacific Design Automation Conf., 2003, pp. 271-276.
27. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay," in Proc. Design Automation Conf., 2003, pp. 348-353.
28. X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway, "Uncertainty-aware circuit optimization," in Proc. Design Automation Conf., 2002, pp. 58-63.
29. J. A. G. Jess, K. Kalafala, S. R. Naidu, C. Visweswariah, and R. H. J. M. Otten, "Statistical timing for parametric yield prediction of digital integrated circuits," in Proc. Design Automation Conf., 2003.
30. L. Scheffer, "Explicit computation of performance as a function of process variation," in Proc. TAU, 2002.
31. private communication Kerry Bernstein, IBM Corp., Burlington, VT, Personal Communication.
32. W. P. Feller, An Introduction to Probability Theory and Its Applications. New York: Wiley, 1970, vol. 1.