Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 295-300

  Bai, Geng ^a   Bobba, Sudhakar ^b   Hajj, Ibrahim N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC POWER SYSTEMS; LOGIC GATES; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS;

STATIC TIMING ANALYSIS;

VLSI CIRCUITS;

EID: 0034846652     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156154     Document Type: Article

References (12)

1. Maximum power supply noise estimation in VLSI circuits via a pareto genetic algorithms
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3. Maximum power supply noise estimation in digital VLSI circuits using multimodal genetic algorithms
4. RC power bus maximum voltage drop estimation in digital VLSI circuit
5. On the general false path problem in timing analysis
6. A path selection algorithm for timing analysis
7. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
8. Estimation of maximum switching activity in digital VLSI circuits
9. Estimation of maximum current envelope for power bus analysis and design
10. Dynamic timing analysis considering power supply noise effects
11. Analysis of performance impact caused by power supply noise in deep submicron devices