Bounded-skew clock and steiner routing

ACM Transactions on Design Automation of Electronic Systems

Volumn 3, Issue 3, 1998, Pages 341-388

  Cong, Jason ^a,d   Kahng, Andrew B ^b   Koh, Cheng Kok ^c   Albert Tsao, C W ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California   (United States)

^c PURDUE UNIVERSITY   (United States)

^d Ultima Interconnect Technology   (United States)

Author keywords

(inter)connection; Algorithms; Boundary merging and embedding; Bounded Skew; Clock tree; Design; Elmore delay; Experimentation; Interior merging and embedding; Low power; Merging region; Merging segment; Pathlength delay; Performance

Indexed keywords

EID: 22644449767     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/293625.293628     Document Type: Article

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