Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2000, Pages 33-38

  Liu, I Min ^a   Chou, Tan Li ^a   Aziz, Adnan ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; EMBEDDED SYSTEMS; TIMING CIRCUITS; TREES (MATHEMATICS); VLSI CIRCUITS;

INTEGRATED DEFERRED-MERGE EMBEDDING (IDME) ALGORITHMS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033702370     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/332357.332370     Document Type: Conference Paper

References (29)