Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 62-67

  Orshansky, Michael ^a   Milor, Linda ^b   Chen, Pinhong ^a   Keutzer, Kurt ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ESilicon Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; TIMING CIRCUITS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; GATES (TRANSISTOR); MATHEMATICAL MODELS; MOSFET DEVICES;

COMBINATIONAL LOGIC BLOCKS; HIGH SPEED DIGITAL CIRCUIT; INTRA-CHIP VARIABILITY; LOCATION DEPENDENTS; PERFORMANCE DEGRADATION; PROCESS PARAMETERS; SPATIAL INFORMATIONS; STATE-OF-THE ART FABRICATIONS;

LOGIC CIRCUITS; INTEGRATED CIRCUIT TESTING;

COMBINATIONAL LOGIC BLOCK; INTRA CHIP VARIABILITY; LARGE CIRCUIT PATH DELAY; TIMING ANALYSIS;

EID: 0034474970     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896452     Document Type: Conference Paper

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