Statistical skew modeling for general clock distribution networks in presence of process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 704-717

  Jiang, Xiaohong ^b   Horiguchi, Susumu ^a,b  

^a IEEE   (Japan)

^b JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Clock distribution network; Clock skew; Maximal clock delay; Process variations; Statistical modeling; Yield

Indexed keywords

CLOCK DISTRIBUTION NETWORKS; STATISTICAL SKEW MODELING;

MATHEMATICAL MODELS; PROCESS CONTROL; STATISTICAL METHODS; VLSI CIRCUITS;

TIMING CIRCUITS;

EID: 0035472944     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953503     Document Type: Article

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