Process variation aware clock tree routing

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 174-181

  Lu, Bing ^a   Hu, Jiang ^b   Ellis, Gary ^c   Su, Haihua ^d  

^a CADENCE DESIGN SYSTEMS   (United States)

^b Texas AandM University   (United States)

^c IBM MICROELECTRONICS   (United States)

^d IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Clock tree synthesis; Interconnect; Physical design; VLSI

Indexed keywords

ALGORITHMS; DATA TRANSFER; DECISION MAKING; INTEGRATED CIRCUIT LAYOUT;

ROUTING;

VLSI CIRCUITS;

EID: 0038040186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640000.640037     Document Type: Conference Paper

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