Worst Case Clock Skew Under Power Supply Variations

ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

Volumn , Issue , 2002, Pages 22-28

  Zhao, Min ^a   Gala, Kaushik ^a   Zolotov, Vladimir ^a   Fu, Yuhong ^a   Panda, Rajendran ^a   Ramkumar, R ^b   Agrawal, Bhuwan ^b  

^a MOTOROLA INC   (United States)

^b Motorola India Pvt Ltd   (India)

Author keywords

Clock network; Clock skew; Power supply noise

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; INDUCTANCE; RELIABILITY; SPURIOUS SIGNAL NOISE;

CLOCK NETWORK;

MICROPROCESSOR CHIPS;

EID: 0141649465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/589412.589416     Document Type: Conference Paper

References (12)

1. Abhijit Dharchoudhury, et.al. "Design and analysis of power distribution networks in PowerPC microprocessors", DAC 1998, June 1998, pp. 738-743.
2. Gregory Steele, et.al., "Full-Chip Verification Methods for DSM Power Distribution Systems", DAC 1998, June 1998, pp. 744-749.
3. A. Chandrakasan, et.al., "Design of High Performance Microprocessor Circuits", IEEE Press, 2001.
4. D.Harris, M.Horowitz, D.Liu, "Timing Analysis Including Clock Skew", IEEE Transactions on CAD, Vol.18, No. 11, Nov l999, pp.1608-1618
5. L.H. Chen, et.al., "Coping with Buffer Delay Change Due to Power and Ground Noise", DAC 2002, June 2002, pp. 860-865.
6. G. Bai, et.al., "Static Timing Analysis Including Power Supply Noise Effect on Propagation delay in VLSI Circuits", DAC 2001, June 2001, pp. 295-300.
7. Y.i-Min Jiang, et.al., "Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices", DAC 1999, June 1999, pp. 760-765.
8. Y.-M. Jiang, et.al., "Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power Supply Noise Effects", IEEE Transactions on CAD, Vol. 20, No. 3, March 2001, pp. 416-425.
9. R. Saleh, et.al.,"Clock Skew Verification in the Presence of IR-Drop in the Power Distribution Network", IEEE Transactions on CAD, Vol. 19, No. 6, June 2000, pp. 635-644.
10. Rajendran Panda, et.al., "Model and analysis for combined package and on-chip power grid simulation", ISLPED 2000, August 2000, pp. 179-184.
11. PrimePower Manual, Synopsys Inc.
12. Kaushik Gala, et.al., "On Chip Inductance Modeling and Analysis", DAC 2000, June 2000, pp. 63 - 68.