Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 168-171

  Liu, Ying ^a   Nassif, Sani R ^a   Pileggi, Lawrence T ^a   Strojwas, Andrzej J ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL POLISHING; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; NUMERICAL METHODS;

CHEMICAL MECHANICAL POLISHING; CLOCK NET; CLOCK SKEW; GIGAHERTZ MICROPROCESSOR; INTERCONNECT VARIATIONS;

MICROPROCESSOR CHIPS;

EID: 0033699258     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/337292.337365     Document Type: Conference Paper

References (7)