Poly-Si thin-film transistors: An efficient and low-cost option for digital operation

IEEE Transactions on Electron Devices

Volumn 54, Issue 11, 2007, Pages 2918-2929

  Li, Jing ^a   Bansal, Aditya ^a,b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Grain boundary (GB); Low pressure chemical vapor deposition (LPCVD); Low temperature polycrystalline silicon (LTPS); Thin film transistor (TFT)

Indexed keywords

GRAIN BOUNDARIES; HYDROGENATION; LOW PRESSURE CHEMICAL VAPOR DEPOSITION; MOSFET DEVICES; OPTIMIZATION; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY; TEMPERATURE;

POLYCRYSTALLINE-SILICON THIN-FILM TRANSISTORS; ULTRALOW-POWER DIGITAL OPERATION;

THIN FILM TRANSISTORS;

EID: 36248935665     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.906940     Document Type: Article

References (33)

1. B. Paul, A. Raychowdhury, and K. Roy, "Device optimization for digital subthreshold logic operation," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 237-247, Feb. 2005.
2. B. Paul and K. Roy, "Device optimization for digital sub-threshold operation," in Proc. IEEE Device Res. Conf., Jun. 2004, pp. 113-114.
3. T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, and N. Konishi, "An LCD addressed by a-Si: H TFTs with peripheral poly-Si TFT circuits," in IEDM Tech. Dig., 1993, pp. 389-392.
4. T. Aoyama, K. Ogawa, Y. Mochizuki, and N. Konishi, "Inverse staggered poly-Si and amorphous Si double structure TFTs for LCD panels with peripheral driver circuit integration," IEEE Trans. Electron Devices vol. 43, no. 5, pp. 701-705, May 1996.
5. S. Jagar, H. Wang, and M. Chan, "Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET," IEEE Trans. Electron Devices, vol. 22, no. 5, pp. 218-220, May 2001.
6. K. Yamaguchi, "Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size," J. Appl. Phys, vol. 89, no. 1, pp. 590-595, Jan. 2001.
7. M. Wang and M. Wong, "Characterization of an individual grain boundary in metal-induced laterally crystallized polycrystalline silicon thin-film devices," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1655-1660, Aug. 2001.
8. V. Subramanian, P. Dankoski, L. Degertekin, B. T. Khuri-Yakub, and K. C. Saraswat, "Controlled two-step solid-phase crystallization for high-performance polysilicon TFTs," IEEE Electron Device Lett., vol. 18, no. 8, pp. 378-381, Aug. 1997.
9. N. Kubo, N. Kusumoto, T. Inushima, and S. Yamazaki, "Characteristics of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method," IEEE Trans. Electron Devices, vol. 41, no. 10, pp. 1876-1879, Oct. 1994.
10. N. Yamauchi, J.-J. J. Hajjar, and R. Reif, "Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film," IEEE Trans. Electron Device, vol. 38, no. 1, pp. 55-60, Jan. 1991.
11. H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang, and P. K. Ko, "Super thin-film transistor with SOICMOS performance formed by a novel grain enhancement method," IEEE Trans. Electron Devices, vol. 47, no. 8, pp. 1580-1586, Aug. 2000.
12. Taurus Device Simulator, Mountain View, CA: Synopsys Inc.
13. J. W. Smith, Y. Macda, and R. S. Iyer, "Disilane-based low thermal budget silicon dioxide chemical vapor deposition process in a single-wafer chamber," Electrochem. Solid-State Lett., vol. 9, no. 4, pp. G141-G143, 2006.
14. P. M. Walker, S. Uno, and II. Mizuta, "Simulation study of the dependence of submicron polysilicon thin-film transistor output characteristics on grain boundary position," Jpn. J. Appl. Phys., vol. 44, no. 12, pp. 8322-8328, 2005.
15. A. J. Walker, S. B. Herner, T. Kumar, and E.-H. Chen, "On the conduction mechanism in polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1856-1866, Nov. 2004.
16. H.-S. Kong and C. Lee, "Two-dimensional simulation study of field-effect operation in undoped poly-Si thin-film transistors," J. Appl. Phys., vol. 78, no. 10, pp. 6122-6131, Nov. 1995.
17. Y. Kitahara, S. Toriyama, and N. Sano, "Statistical study of subthreshold characteristics in polycrystalline silicon thin-film transistors," J. Appl. Phys., vol. 94, no. 12, pp. 7789-7795, Dec. 2003.
18. M. Walker, H. Mizuta, S. Uno, Y. Furuta, and D. G. Hasko, "Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel," IEEE Trans. Electron Devices, vol. 5 1, no. 2, pp. 212-219, Feb. 2004.
19. A. A. Orouji and M. J. Kumar, "A new poly-Si TG-TFT with diminished pseudosubthreshold region: Theoretical investigation and analysis," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1815-1820, Aug. 2005.
20. W. B. Jackson, N. M. Johnson, and D. K. Biegelsen, "Density of gap states f silicon grain boundaries determined by optical absorption," Appl. Phys. Lett., vol. 43, no. 2, pp. 195-197, Jul. 1983.
21. H. N. Chern, C. L. Lee, and T. Fu, "Correlation of polysilicon thin-film transistor characteristics to defect states via thermal annealing," IEEE Trans. Electron Devices, vol. 41, no. 3, pp. 460-462, Mar. 1994.
22. I.-W. Wu, T.-Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, "Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation," IEEE Electron Device Lett., vol. 12, no. 4, pp. 181-183, Apr. 1991.
23. G. Fortunato, D. B. Meakin, P. Migliorato, and P. G. Le Comber, "Field-effect analysis for the determination of gap state density and Fermi-level temperature dependence in polycrystalline silicon," Philos. Mag. B., vol. 57, p. 573, 1988.
24. K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989.
25. R.-H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, Jul. 1992.
26. K. Suzuki, Y. Tosaka, and T. Sughii, "Analytical threshold voltage model for short channel n+ - p+ double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 43, no. 5, pp. 732-738, May 1996.
27. F. V. Farmakis, J. Brini, G. Kamarinos, C. T. Angelis, C. A. Dimitriadis, and M. Miyasaka, "On-current modeling of large-grain polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 701-706, Apr. 2001.
28. P. Ranade, Y. -K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable work function molybdenum gate technology for FDSOI-CMOS," in IEDM Tech. Dig., Dec. 2002, pp. 363-366.
29. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, UX.: Cambridge Univ. Press, 1998.
30. The International Technology Roadmap for Semiconductors. SanJose, CA: Semicond. Ind. Assoc., 1999.
31. J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys., vol. 53, no. 2, pp. 1193-1202, Feb. 1982.
32. S. Jagar, C. F. Cheng, S. Zhang, H. Wang, M. C. Poon, C. W. Kok, and M. Chan, "A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film," IEEE Trans. Electron Devices, vol. 50, no. 4, Apr. 2003.
33. J. G. Fossum, A. O. Conde, H. Shichijo, and S. K. Banerjee, "Anomalous leakage current in LPCVD polysilicon MOSFETs," IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1878-1884, Sep. 1985.