Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

IEEE Electron Device Letters

Volumn 22, Issue 5, 2001, Pages 218-220

  Jagar, Singh ^b   Wang, Hongmei ^b   Chan, Mansun ^a,b  

^a IEEE

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

3 D VLSI; MILC; Polysilicon; SOI; Thin film transistor

Indexed keywords

GRAIN BOUNDARIES; LEAKAGE CURRENTS; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THIN FILM TRANSISTORS; THRESHOLD VOLTAGE;

LARGE-GRAIN POLYSILICON-ON-INSULATOR (LPSOI) FILMS;

MOSFET DEVICES;

EID: 0035337186     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.919234     Document Type: Article

References (16)