On-current modeling of large-grain polycrystalline silicon thin-film transistors

IEEE Transactions on Electron Devices

Volumn 48, Issue 4, 2001, Pages 701-706

  Farmakis, Filippos V ^a,b   Brini, Jean ^b   Kamarinos, George ^b   Angelis, Constantinos T ^c   Dimitriadis, Charalambos A ^a,c   Miyasaka, M ^d  

^a IEEE   (France)

^b Grenoble INP Phelma   (France)

^c ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

^d SEIKO EPSON CORPORATION   (Japan)

Author keywords

Grain boundaries; Modeling; Polycrystalline silicon; Thin film transistors

Indexed keywords

LASER ANNEALING;

ANNEALING; EXCIMER LASERS; GRAIN BOUNDARIES; POLYSILICON; SEMICONDUCTOR DEVICE MODELS; THERMAL EFFECTS;

THIN FILM TRANSISTORS;

EID: 0035308163     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.915695     Document Type: Article

References (15)

1. Conductivity behavior in polycrystalline semiconductor thin film transistors
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5. An analytical model for the above-threshold characteristics of polysilicon thin-film transistors
6. Modeling of laser-annealed polysilicon TFT characteristics
7. Two-dimensional simulation study of field-effect operation in undoped poly-Si thin-film transistors
8. Two-dimensional numerical simulation of solid-phase-crystallized polysilicon thin-film transistor characteristics
9. Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film
10. Narrow width effects of bottom-gate polysilicon thin film transistors
11. An analytical grain-barrier height model and its characteristics for intrinsic poly-Si thin-film transistor
12. Analytical modeling of the MOS transistor
13. Thin film transistors on 50-nm-thick polysilicon films obtained by a combination of Solid Phase Crystallization and Excimer laser annealing
14. Grain and grain-boundary control on transfer characteristics of large-grain polycrystalline silicon thin film transistors