A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

IEEE Transactions on Electron Devices

Volumn 50, Issue 4, 2003, Pages 1103-1108

  Jagar, Singh ^a   Cheng, C F ^a   Zhang, Shengdong ^a   Wang, Hongmei ^a,b   Poon, M C ^a   Kok, C W ^a   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b MICRON TECHNOLOGY INC   (United States)

Author keywords

BSIM and SPICE; GBs; MILC; Polysilicon; TFT modeling and circuit simulation; Thin film transistors

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CRYSTAL MICROSTRUCTURE; CRYSTALLIZATION; POLYSILICON;

POLYSILICON FILMS;

THIN FILM TRANSISTORS;

EID: 0037480751     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.812487     Document Type: Article

References (22)

1. I. W. Wu, "Cell design considerations for high-aperture-ratio direct-view and projection poly-Si TFT-LCD's," in Dig. Tech. Papers, SID, 1995, pp. 19-22.
2. Y. Takao, H. Shimada, N. Suzuki. Y. Matsukawa, and N. Sasaki, "Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET," IEEE Trans. Electron Devices, vol. 39, pp. 2147-2152, Sept. 1992.
3. T. Noguchi, "Appearance of single-crystalline properties in fin-patterned Si TFTs by solid phase crystallization," Jpn. J. Appl. Phys., pt. 2, vol. 32, no. 11A, pp. 1584-1587, Nov. 1993.
4. N. Kubo, N. Kusumoto, T. Insushima, and S. Yamazaki, "Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method," IEEE Trans. Electron Devices, vol. 40, pp. 1876-1879, Oct. 1994.
5. S.-W. Lee and S.-K. Joo, "Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization," IEEE Electron Device Lett., vol. 17, pp. 160-162, Apr. 1996.
6. Z. Meng, M. Wang, and M. Wong, "High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin-film transistors for system-on-panel applications," IEEE Trans. Electron Devices, vol. 47, pp. 404-409, Feb. 2000.
7. A. Wang and K. C. Saraswat, "A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors," IEEE Trans. Electron Devices, vol. 47, pp. 1035-1043, May 2000.
8. F. V. Farmakis, J. B. Brini, G. Kamarinos, C. T. Angelis, C. A. Dimitrias, and M. Miyaska, "On-current modeling of large-grain polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 48, pp. 701-706, Apr. 2001.
9. P. Lin, J. Guo, and C. Wu, "A Quasi-two-dimensional analytical model for the turn on characteristics of poly-Si thin-film transistor," IEEE Trans. Electron Devices, vol. 37, pp. 666-674, Mar. 1990.
10. S. S. Chung, D. C. Chen, C. T. Cheng, and C. F. Yen, "A physically-based built-in spice poly-Si TFT model for circuit simulation and reliability evaluation," in IEDM Tech. Dig., 1996, pp. 139-142.
11. F. Qian, D. M. Kim, H. K. Park, and J. L. Scahitano, "Inversion-Mode MOSFET's in polycrystalline silicon thin-film: Characterization and modeling," IEEE Trans. Electron Devices, vol. 35, pp. 2439-2449, Dec. 1987.
12. G. A. Armsstrong, S. Uppal, S. D. Brohteroton, and J. R. Ayres, "Modeling of laser-annealed poly-Si TFT characteristics," IEEE Electron Device Lett., vol. 18, pp. 315-318, July 1997.
13. [Online]. Available: http://www-device.eecs.berkeley.edu/̃bsimsoi.
14. [Online]. Available: http://www.eigroup.org/cmc.
15. S. Jagar, H. Wang, and M. Chan, "Effects of longitudinal and latitudinal GBs on the performance of large-grain poly-Si MOSFETs," IEEE Electron Device Lett., vol. 22, pp. 215-217. May 2001.
16. H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang, and P. K. Ko, "Super thin-film transistor with SOI CMOS performance formed by a novel grain-enhancement method," IEEE Trans. Electron Devices, vol. 47, pp. 1580-1586, Aug. 2000.
17. J. Levinson, F. R. Shepherd, P. J. Scanion, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin-film transistor," J. Appl. Phys., vol. 53, pp. 1193-1202, Feb. 1982.
18. M. Wang, Z. Meng, and M. Wong, "Anisotropic conduction behavior in metal-induced laterally crystallized polycrystalline silicon thin-films," Appl. Phys. Lett., vol. 76, no. 4, pp. 448-450, Jan. 2000.
19. G. Bhat, H. Kwok, and M. Wong, "Plasma hydrogenation of metal-induced laterally crystallized thin-film transistors," IEEE Electron Device Lett., vol. 21, pp. 73-75, Feb. 2000.
20. Z. H. Liu, C. Hu, J. H. Huang, T. Y. Chan, M. C. Jeng, P. K. Ko, and Y. C. Cheng, "Threshold voltage model for deep-submicrometer MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 86-95, Jan. 1993.
21. Y.-H. Cheng, M. Chan, K. Chen, J. Chen, J. H. Huang, Z. H. Liu, M. C. Jeng, K. Hui, P. K. Ko, and C. Hu, "BSIM3 version 3.0 manual," Univ. California, Berkeley, CA, July 1995.
22. S. Jagar, H. Wang, and M. Chan, "Design methodology of the high performance large-grain poly-Si MOSFET," IEEE Trans. Electron Devices, vol. 49, pp. 795-801, May 2002.