Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 415-422

  Yoneda, Tomokazu ^a   Uchiyama, Tetsuo ^b   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b CANON INC   (Japan)

Author keywords

Consecutive testability; Design for testability; System on a chip; Test access mechanism; Test scheduling

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS;

TEST SCHEDULING;

DESIGN FOR TESTABILITY;

EID: 0142153717     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Y.Zorian, E.J.Marinissen and S.Dey, "Testing embedded-core based system chips," Proc. 1998 Int. Test Conf., pp.130-143, Oct. 1998.
2. S.Bhatia, T.Gheewala and P.Varma, "A unifying methodology for intellectual property and custom logic testing," Proc. 1996 Int. Test Conf., pp.639-648, Oct. 1996.
3. T.Ono, K.Wakui, H.Hikima, Y.Nakamura and M.Yoshida, "Integrated and automated design-for-testability implementation for cell-based ICs," Proc. 6th Asian Test Symp., pp.122-125, Nov. 1997.
4. P.Varma and S.Bhatia, "A structured test re-use methodology for core-based system chips," Proc. 1996 Int. Test Conf., pp.294-302, Oct. 1998.
5. E.Marinissen, R.Arendsen, G.Bos, H.Dingemanse, M.Lousberg and C.Wouters, "A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores," Proc. 1998 Int. Test Conf., pp.284-293, Nov. 1998.
6. N.A.Touba and B.Pouya, "Testing embedded cores using partial isolation rings," Proc. 15th VLSI Test Symp., pp.10-16, May 1997.
7. L.Whetsel, "An IEEE 1149.1 based test access architecture for ICs with embedded cores, " Proc. 1997 Int. Test Conf., pp.69-78, Nov. 1997.
8. M.Nourani and C.A.Papachristou, "Structural fault testing of embedded cores using pipelining," Journal of Electronic Testing:Theory and Applications 15, pp.129-144 1999.
9. I.Ghosh, S.Dey, and N.K.Jha, " A fast and low cost testing technique for core-based system-chips," IEEE Trans. on CAD, vol.19, no.8, pp.863-877, Aug. 2000.
10. S.Ravi, G.Lakshminarayana, and N.K.Jha, " Testing of Core-Based Systems-on-a-Chip," IEEE Trans. on CAD, vol.20, no.3, pp.426-439, Mar. 2001.
11. K.Chakrabarty, "Design of System-on-a-Chip Test Access Architectures Using Integer Linear Programming," Proc. 18th VLSI Test Symp., pp.127-134, May 2000.
12. K.Chakrabarty, "Design of System-on-a-Chip Test Access Architectures under Place-and-Route and Power Constraints," Proc. 37th Design Automation Conf., pp.432-437, June 2000.
13. Erik Larsson, Klas Avidsson, Hideo Fujiwara and Zebo Peng, "Integrated Test Scheduling, Test Parallelization and TAM Design," Proc. 11th Asian Test Symp., pp.397-404, Nov. 2002.
14. Tomokazu Yoneda and Hideo Fujiwara, "Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores," Journal of Electronic Testing: Theory and Applications (JETTA) Special Issue on Plug-and-Play Test Automation for System-on-a-Chip, Vol. 18, No. 4/5, pp.487-501, Aug./0ct. 2002.
15. K.Chakrabarty, R.Mukherjee and A.Exnicios, "Synthesis of Transparent Circuits for Hierarchical and System-on-a-Chip Test," Proc. IEEE International Conference on VLSI Design, pp.431-436, Jan. 2001.
16. Tomokazu Yoneda and Hideo Fujiwara, "Design for Consecutive Transparency of Cores in System-on-a-Chip," proc. 21st VLSI Test Symp.(VTS'03), pp.287-292, Apr. 2003.
17. IEEE P1500 web site, http://grouper.ieee.org/groups/1500/.
18. M.Berkelaar, lp-solve, Eindhoven University of Technology, The Netherlands, ftp://ftp.ics.ele.tue.nl/pub/lp_solve.
19. V.Iyengar and K.Chakrabarty, "Precedence-based, preemptive, and power-constrained test schduling for system-on-a-chip," Proc. IEEE VLSI Test Symposium (VTS'01), pp.42-47, April 2001.