Integrated and automated design-for-testability implementation for cell-based ICs

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 122-125

  Ono, Toshinobu ^a   Wakui, Kazuo ^a   Hikima, Hitoshi ^a   Nakamura, Yoshiyuki ^a   Yoshida, Masaaki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY (DFT);

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0031353042     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. H. Yamauchi, M. Yoshida, T. Ono, Y. Umeki and N. Takase, "Hardware and Software Approach for IDDQ Test", International Workshop on IDDQ Testing, pp.26-29, 1995.
2. S. T. Chakradhar, V. D. Agrawal and S. G. Rothweiler, "A Transitive Closure Algorithm for Test Generation", IEEE Trans. CAD, vol.12, pp.1015-1028, 1993.