A TMR scheme for SEU mitigation in scan flip-flops

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 905-910

  Oliveira, Roystein ^a   Jagirdar, Aditya ^a   Chakraborty, Tapan J ^b  

^a RUTGERS UNIVERSITY   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; INTEGRATED CIRCUITS; MICROELECTRONICS; TRANSISTORS;

FUNCTIONAL DATA; SOFT ERRORS;

FLIP FLOP CIRCUITS;

EID: 34548127914     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.25     Document Type: Conference Paper

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