An ultra-low-power, radiation-tolerant reed solomon encoder for space applications

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 631-634

  Gambles, J ^a   Miles, L ^a   Hass, J ^a   Smith, W ^a   Whitaker, S ^a   Smith, B ^b  

^a UNIVERSITY OF IDAHO   (United States)

^b PicoDyne Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; SPACE APPLICATIONS; THRESHOLD VOLTAGE;

LOGIC ARCHITECTURE; REED-SOLOMON ENCODER; ULTRA-LOW-POWER PROCESS;

ENCODING (SYMBOLS);

EID: 0242696031     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. J. Rabaey and M. Pedram (editors), Low Power Design Methodologies, Kluwer Academic Publishers, 1996, p. 25.
3. T. Ma and P. Dressendorfer, Ionizing Radiation Effects in MOS Devices & Circuits, New York, NY, John Wiley & Sons, 1989, Chap. 9.
4. J. Osborn, R. Lacoe, D. Mayer, and G. Yabiku, "Total Does Hardness of Three Commercial CMOS Microelectronics Foundries", IEEE Transactions On Nuclear Science, Vol. 45, No. 3, June 1998, pp. 1458-1463.
5. J. Canaris, S. Whitaker, and K. Cameron, "Mechanism for Preventing Radiation Induced Latchup in CMOS Integrated Circuits", U.S. Patent 5,406,513, Apr. 11, 1995.
6. M.A. Xapsos, G.P. Summers, and E.M. Jackson. "Enhanced Total Ionizing Dose Tolerance of Bulk CMOS Transistors Fabricated for Ultra-Low Power Applications", IEEE Transactions On Nuclear Science, Vol. 46, No. 6, Dec. 1999, pp. 1697-1701.
7. Q. Shi and G. Maki, "New Design Techniques for SEU Immune Circuits", Proceedings of the 9th NASA Symposium on VLSI Design, Albuquerque, NM, Nov. 2000, pp. 7.4.1-7.4.16